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A Low Power Dissipation Technique for a Low Voltage OTA

机译:A Low Power Dissipation Technique for a Low Voltage OTA

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This paper proposes a novel low power dissipation technique for alow voltage operation with a class AB input stage is not suitable fora low voltage operation (±1.5 V supply voltages), because it usescomposite transistors (referred to CMOS pair) which has a largethreshold voltage. On the other hand, the tail-current type OTA needsa large tail-current value to obtain a sufficient input range at theexpense of power dissipation. Therefore, the conventionaltail-current type OTA has a trade-off between the input range and thepower dissipation to the tail-current value. The trade-off can beeliminated by the proposed technique.

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