An analytic evaluation on soft error immunity enhancement due to temporal triplication

摘要

>Chip-level soft error rate is increasing owing to the device miniaturisation and larger-scale integration. Soft errors are one of the major factors that degrade the reliability of integrated circuits, and soft error aware design is demanded for applications that cannot allow any failures. As one of the soft error countermeasures, spatial redundancy has been widely studied and adopted in real products because of its small speed overhead and easiness of implementation. On the other hand, temporal redundancy, which is another well-known technique, is rarely adopted in practical applications and its usefulness is not comparatively evaluated. This paper analytically evaluates the soft error immunity enhancement, thanks to temporal triplication. The evaluation result shows that the failure rate reduction of the temporal triplication is comparable to that of the spatial triplication in the supposed pipeline hardware and computation model.