Design of sampled analog wavelet processor architecture for cochlear implant application

摘要

This paper presents the design of sampled analog wavelet processor architecture for cochlear implant application using discrete Haar wavelet transform. Basic element of sampled analog wavelet processor architecture is operational amplifier based switched capacitor integrator circuit. This architecture distributes input signal frequencies into different predefined frequency band and based on cochlear sensitivity region for different frequencies by using arbitrary tree structure. The presented architecture is beneficial in terms of processing time of input signal, area and complexity by avoiding quantization and encoding process part of data converter circuits. Simulation results for this architecture is carried out with CMOS 90 nm technology.