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Fault-tolerant design of mutually coupled neural networks based on the duplication of neurons with the higher functionality

机译:基于较高功能的神经元重复的相互耦合神经网络的容错设计

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摘要

Since the integration technology has been well developed to implement a large number of operational Units in a LSI chip, it is becoming possible to use such neuro-chips for highly parallel information processing. However we may encounter problems in implementing neural networks in neuro-chips, because constituent components of a neural network are complicated and further a neural network has numerous coupling elements among its constituent components. Thus, we cannot ignore the possibility that neuro-chips may suffer the occurrence of their faults. In this study, we propose a new simplified model of neural networks, in which each neuron with the higher functionality is duplicated to enhance the fault tolerance.
机译:由于集成技术已经开发出了在LSI芯片中实现了大量的操作单元,因此可以使用这种神经芯片来获得高度并行信息处理。 然而,我们可能遇到在神经芯片中实现神经网络的问题,因为神经网络的组成部分复杂,并且进一步的神经网络在其组成部件中具有许多耦合元件。 因此,我们不能忽视神经芯片可能遭受故障的可能性。 在这项研究中,我们提出了一种新的神经网络简化模型,其中具有更高功能的每个神经元被复制以增强容错能力。

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