Single-Event-Hardened Timing Generator for waveform digitizer based readout electronics

摘要

Waveform digitizer, the soul of readout electronics in the radiation detectors performing a multitude of functions has to evade the impact of single-event transients in its timing reference. The propagation of transients from the timing generator to the analog memory causes timing non-linearity due to variation in the inverter delay responsible for the sampling speed leading to catastrophic failure of the waveform sampler. The presented timing generator using mixed-signal delay-locked loop implements the triple combination of the body-feed technique allowing railto- rail operation for delay control, the pseudo differential structure regulating duty cycle reduces the jitter and also optimize the linear operating range of the voltage-controlled-delay-line, and the mixed-signal delay-locked loop embedded with dual-edge synchronization enhances the mitigation of single-event upsets. The simulation results at the circuit level using 180 nm and 90 nm CMOS PDKs show a 28% increase in the linear operating range and bettering jitter performance of the mixed-signal delay-locked loop in comparison to the fully differential voltage-controlled-delay-line based delay-locked loop. Furthermore, there is only negligible variance between the irradiated and non-irradiated values for delay interval of each sampling cell and cell-to-cell gain variation in the analog memory of the waveform sampler.