ECC design strategy targeting area optimization in reconfigurable device (FPGA) using VLSI Technique

摘要

Forward error correction (FEC) plays an important role in the field of telecommunication and information theory as it improves the capacity of a channel. It has been observed that Reed Solomon Error Corrector is a powerful method for error detection and correction. Error Correction codes (ECC) are a mean of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. This research paper describes new design strategy targeting area optimization in reconfigurable device (FPGA). Area optimization is a major issue as smaller components allow for better system adaption, which is an expected feature of reconfigurable system for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) targeting an FPGA platform. The research work investigates traditional alternatives for the encoder implementation, introduces the new architecture of the error corrector behind the proposed approach, describes the design process and discusses the area figures reached by the new design.