Implementation of Fusion Technique with Modified Booth Recoder

摘要

Complex Arithmetic operations were carried out in the applications of DSP. The speed of Addition and multiplication has to be increased. A new concept of Adder Multiplier is implemented by using Sum to Modified Booth algorithm bits were generated in its Modified Booth form. The generated partial products were reduced by using Wallace Tree multiplier. Without degrading the performance the power consumption is reduced by using compressor. The 4:2 compressors is chosen which reduces the partial product 4 to 2. The parallel multiplier with the compressor increases the speed, decreases delay thereby reducing power consumption. The output of compressor is given to CLA adder to obtain the final result.