A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

摘要

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 mu m technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.