A new multiple transistor parameter design methodology based on a SoC performance evaluation function

摘要

For scaled low voltage CMOS, V{sub}(TH), V{sub}(DD) and T{sub}(OX) must be highly optimized to achieve both low power and high speed. To perform such optimization for complex system-on-a-chip's (SoCs) consisting of multiple blocks, and using multiple V{sub}(TH), V{sub}(DD) and T{sub}(OX), a new performance evaluation function is proposed. It was confirmed that optimized assignment of multiple V{sub}(TH), V{sub}(DD) and T{sub}(OX) can be automatically determined by simply evaluating or searching for the minimum of the function. It was also found that the use of multiple parameters is particularly effective for SoCs consisting of circuit blocks with different speed requirements.