Register access scheduling logic for superscalar processors with multi-bank register file

摘要

Compared with conventional multi-port register files, multi-bank register file can realise smaller chip size, faster access time, and lower power consumption. According to the result of layout data, the multi-bank register achieved to reduce 70% of chip size, 49% of access time, and 81% of power consumption. However, the multi-bank register file could cause a performance degradation due to possible bank conflicts. This paper proposes a resolution to reduce access conflicts for superscalar processors with the multi-bank register file. We also implemented register access queue for evaluation. By evaluation result, the validity of this method was confirmed.