Low-Power and High Speed Techniques Due to Optimization of Short-Circuit Currents for CMOS Digital Circuits

摘要

A technique that can reduce active power dissipation (P{sub}t) and minimize delay-time (t{sub}(dt)) in CMOS logic circuits has been developed by examining a 0.18-μm CMOS digital circuit. This circuit consisited of a three-stage inverter circuit, that is, a single inverter pre-driver stage, m-parallel inverter driver stage and JV-parallel inverter load stage. By both a SPICE analysis and experimental results obtained by fabricated devices, it was found that both minimum P{sub}t and t{sub}(dt) were obtained by choosing m of N{sup}(1/2){ = (m×n){sup}(1/2) = n}.