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Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes

机译:时钟树的后优化,用于在45 nm及以下技术节点中动态降低时钟树功率

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Power consumption of the clock tree dominates over 40% of the total power in modern high performance wireless system on chip (SOC) designs, hence measures must be taken to optimize the clock tree power. One of the most effective methods is based on clock gating where the clock is switched off for the different idle modules inside the SOC. However, the improvements are often limited by the register placement and clock routing. In this work, we propose a placement scheme, which optimizes the wire length from the last leaf node buffers to the registers. We also navigate and move the registers during post clock tree optimizations to reduce the clock tree power without impacting the timing and physical design rule violations. Experimental results show that our approach is able to reduce clock tree power by almost 17%.
机译:在现代高性能无线片上系统(SOC)设计中,时钟树的功耗占总功耗的40%以上,因此必须采取措施来优化时钟树的功耗。最有效的方法之一是基于时钟门控,其中针对SOC内部的不同空闲模块关闭时钟。但是,这些改进通常受到寄存器放置和时钟路由的限制。在这项工作中,我们提出了一种布局方案,该方案可以优化从最后一个叶子节点缓冲区到寄存器的连线长度。我们还在后期时钟树优化过程中导航和移动寄存器,以减少时钟树的功耗,而不会影响时序和违反物理设计规则。实验结果表明,我们的方法能够将时钟树的功耗降低近17%。

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