Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

摘要

Multi-processor systems need interconnection networks (INs) in order to make the connection among the processors, memory modules, and nodes. Bus interconnection network is the simplest and least expensive one among all the INs. Therefore, bus network is easily understood and preferred by manufactures for implementation. However, a bus network is inherently a non-fault tolerant and blocking network. To cope with these problems, a solution is to use several buses in parallel on a network. Based on this idea, various schemes can be designed for a bus network: (1) Multiple-bus with full bus-memory connection, (2) Multiple-bus with single bus-memory connection, (3) Multiple-bus with partial bus-memory connection, and (4) Multiple-bus with class-based memory connection. On the other hand, a metric for the efficiency of fault-tolerant systems is its reliability. Although, there is no detailed analysis of the reliability of bus-based networks, this paper presents accurate and complete reliability analysis of bus-based networks to achieve these aims: (1) Determining the most efficient design of bus-based networks in terms of reliability, cost-effectiveness, and blocking issues, (2) Providing new methods for evaluating the performance of bus-based networks.