Simultaneous Multithreading Fault Tolerance Processor

摘要

Transient fault detection mechanism is added to simultaneous multithreading architecture By exploiting both IIP (Instruction Level Parallelism) and ILP (Thread Level Parallelism), Simultaneous Multithreading(SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchilecture takes only40%-61% longer than running a single version of the program The new instruction fetch algorithm enhances the performance by 0.4% approx 1 % to most of the benchmarks we choose randomly.