掌桥科研
一站式科研服务平台
科技查新
收录引用
专题文献代查
外文数据库(机构版)
更多产品
首页
成为会员
我要充值
退出
我的积分:
中文会员
开通
中文文献批量获取
外文会员
开通
外文文献批量获取
我的订单
会员中心
我的包量
我的余额
登录/注册
文献导航
中文期刊
>
中文会议
>
中文学位
>
中国专利
>
外文期刊
>
外文会议
>
外文学位
>
外国专利
>
外文OA文献
>
外文科技报告
>
中文图书
>
外文图书
>
工业技术
基础科学
医药卫生
农业科学
教科文艺
经济财政
社会科学
哲学政法
其他
工业技术
基础科学
医药卫生
农业科学
教科文艺
经济财政
社会科学
哲学政法
其他
自然科学总论
数学、物理、化学、力学
天文学、地球科学
生物科技
医学、药学、卫生
航空航天、军事
农林牧渔
机械、仪表工业
化工、能源
冶金矿业
电子学、通信
计算机、自动化
土木、建筑、水利
交通运输
轻工业技术
材料科学
电工技术
一般工业技术
环境科学、安全科学
图书馆学、情报学
社会科学
其他
马克思主义、列宁主义、毛泽东思想、邓小平理论
哲学、宗教
社会科学总论
政治、法律
军事
经济
文化、科学、教育、体育
语言、文字
文学
艺术
历史、地理
自然科学总论
数理科学和化学
天文学、地球科学
生物科学
医药、卫生
农业科学
工业技术
交通运输
航空、航天
环境科学、安全科学
综合性图书
自然科学总论
数学、物理、化学、力学
天文学、地球科学
生物科技
医学、药学、卫生
航空航天、军事
农林牧渔
机械、仪表工业
化工、能源
冶金矿业
电子学、通信
计算机、自动化
土木、建筑、水利
交通运输
轻工业技术
材料科学
电工技术
一般工业技术
环境科学、安全科学
图书馆学、情报学
社会科学
其他
自然科学总论
数学、物理、化学、力学
天文学、地球科学
生物科技
医学、药学、卫生
航空航天、军事
农林牧渔
机械、仪表工业
化工、能源
冶金矿业
电子学、通信
计算机、自动化
土木、建筑、水利
交通运输
轻工业技术
电工技术
一般工业技术
环境科学、安全科学
图书馆学、情报学
社会科学
其他
自然科学总论
数学、物理、化学、力学
天文学、地球科学
生物科技
医学、药学、卫生
航空航天、军事
农林牧渔
机械、仪表工业
化工、能源
冶金矿业
电子学、通信
计算机、自动化
土木、建筑、水利
交通运输
轻工业技术
材料科学
电工技术
一般工业技术
环境科学、安全科学
图书馆学、情报学
社会科学
其他
美国国防部AD报告
美国能源部DE报告
美国航空航天局NASA报告
美国商务部PB报告
外军国防科技报告
美国国防部
美国参联会主席指示
美国海军
美国空军
美国陆军
美国海军陆战队
美国国防技术信息中心(DTIC)
美军标
美国航空航天局(NASA)
战略与国际研究中心
美国国土安全数字图书馆
美国科学研究出版社
兰德公司
美国政府问责局
香港科技大学图书馆
美国海军研究生院图书馆
OALIB数据库
在线学术档案数据库
数字空间系统
剑桥大学机构知识库
欧洲核子研究中心机构库
美国密西根大学论文库
美国政府出版局(GPO)
加利福尼亚大学数字图书馆
美国国家学术出版社
美国国防大学出版社
美国能源部文献库
美国国防高级研究计划局
美国陆军协会
美国陆军研究实验室
英国空军
美国国家科学基金会
美国战略与国际研究中心-导弹威胁网
美国科学与国际安全研究所
法国国际关系战略研究院
法国国际关系研究所
国际宇航联合会
美国防务日报
国会研究处
美国海运司令部
北约
盟军快速反应部队
北约浅水行动卓越中心
北约盟军地面部队司令部
北约通信信息局
北约稳定政策卓越中心
美国国会研究服务处
美国国防预算办公室
美国陆军技术手册
一般OA
科技期刊论文
科技会议论文
图书
科技报告
科技专著
标准
其它
美国卫生研究院文献
分子生物学
神经科学
药学
外科
临床神经病学
肿瘤学
细胞生物学
遗传学
公共卫生&环境&职业病
应用微生物学
全科医学
免疫学
动物学
精神病学
兽医学
心血管
放射&核医学&医学影像学
儿科
医学进展
微生物学
护理学
生物学
牙科&口腔外科
毒理学
生理学
医院管理
妇产科学
病理学
生化技术
胃肠&肝脏病学
运动科学
心理学
营养学
血液学
泌尿科学&肾病学
生物医学工程
感染病
生物物理学
矫形
外周血管病
药物化学
皮肤病学
康复学
眼科学
行为科学
呼吸学
进化生物学
老年医学
耳鼻喉科学
发育生物学
寄生虫学
病毒学
医学实验室检查技术
生殖生物学
风湿病学
麻醉学
危重病护理
生物材料
移植
医学情报
其他学科
人类生活必需品
作业;运输
化学;冶金
纺织;造纸
固定建筑物
机械工程;照明;加热;武器;爆破
物理
电学
人类生活必需品
作业;运输
化学;冶金
纺织;造纸
固定建筑物
机械工程;照明;加热;武器;爆破
物理
电学
马克思主义、列宁主义、毛泽东思想、邓小平理论
哲学、宗教
社会科学总论
政治、法律
军事
经济
文化、科学、教育、体育
语言、文字
文学
艺术
历史、地理
自然科学总论
数理科学和化学
天文学、地球科学
生物科学
医药、卫生
农业科学
工业技术
交通运输
航空、航天
环境科学、安全科学
综合性图书
主题
主题
题名
作者
关键词
摘要
高级搜索 >
外文期刊
外文会议
外文学位
外国专利
外文图书
外文OA文献
中文期刊
中文会议
中文学位
中国专利
中文图书
外文科技报告
清除
历史搜索
清空历史
首页
>
外文会议
>
其他
>
Symposium on Integrated Circuits and Systems Design
Symposium on Integrated Circuits and Systems Design
召开年:
召开地:
出版时间:
-
会议文集:
-
会议论文
热门论文
全部论文
全选(
0
)
清除
导出
1.
Issues in parallelizing multigrid-based substrate model extraction and analysis
机译:
并行化多基于基于多基体的基于基于基于基于基于模型的提取和分析的问题
作者:
Silva J.M.S.
;
Silveria L.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
circuit complexity;
differential equations;
grid computing;
circuit simulation;
coupled circuits;
parallel processing;
substrates;
integrated circuit modelling;
multigrid based substrate model extraction;
substrate model analysis;
coupling effect;
mixed signal systems;
fast switching digital blocks;
high precision sensible analog circuitry;
miniaturization effect;
IC complexity;
distributed computing;
parallelization;
generic computations;
substrate coupling simulation;
2.
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
机译:
基于实时LUT的网络拓扑,用于动态和部分FPGA自我重新配置
作者:
Heubner M.
;
Becker T.
;
Becker J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
integrated logic circuits;
field programmable gate arrays;
network topology;
table lookup;
electronic engineering computing;
real time look up table;
network topology;
Xilinx XC2V3000 FPGA;
run time reconfiguration;
TBUF element;
routing tool;
automatic modular design flow;
3.
Improving mixed-single SOC testing: a power-aware reuse-based approach with analog BIST
机译:
改善混合单SoC测试:基于动力感知的重用基于模拟BIST的方法
作者:
Andrade A. Jr.
;
Cota E.
;
Lubaszewski M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
built-in self test;
system-on-chip;
mixed analogue-digital integrated circuits;
integrated circuit testing;
mixed signal SoC testing;
power aware reuse based approach;
analog BIST;
cost effective test solution;
global system testing time;
digital blocks;
analog signals testing;
4.
PADReH - a framework for the design and implementation of dynamically and partially reconfigurable systems
机译:
Padreh - 动态和部分可重新配置系统的设计和实现的框架
作者:
Carvalho E.
;
Calazans N.
;
Briao E.
;
Moraes F.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
reconfigurable architectures;
field programmable gate arrays;
logic design;
PADReH;
dynamically reconfigurable system;
partially reconfigurable system;
execution time;
hardware reconfiguration process;
partial bitstream;
mainstream technology;
5.
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic
机译:
模型和原型动态可重构系统,用于通过重写逻辑有效计算动态规划方法
作者:
Ayala-Rincon M.
;
Jacobi R.P.
;
Carvalho L.G.A.
;
Llanos C.H.
;
Hartenstein R.W.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
rewriting systems;
systolic arrays;
reconfigurable architectures;
dynamic programming;
field programmable gate arrays;
hardware description languages;
computational complexity;
digital systems;
software prototyping;
modeling;
prototyping;
dynamically reconfigurable systems;
dynamic programming;
rewriting-logic environments;
reconfigurable systolic arrays;
computational problems;
reconfigurable systolic architectures;
digital systems;
global sequence alignment;
local sequence alignment;
Smith-Waterman algorithm;
approximate string matching;
longest common subsequence;
VHDL;
rewriting-logic based abstract models;
FPGA;
APEX family;
6.
RTL power estimation and optimization
机译:
RTL功率估计和优化
作者:
Macii E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
electronic design automation;
power consumption;
optimisation;
integrated circuit design;
circuit CAD;
RTL power estimation;
power optimization;
power consumption;
electronic systems;
mobile telecom;
desktop computers;
portable computers;
nanometer technology;
ambient intelligence;
sensor networks;
design process;
state of the art techniques;
data path macros;
steering logic;
memory hierarchy;
bus interface synthesis;
clock gating strategy;
clock tree planning;
CAD tools;
EDA market;
7.
Statistical analysis and design: from picoseconds to probabilities
机译:
统计分析和设计:从PICOSECONDS到概率
作者:
Visweswariah C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
statistical analysis;
probability;
timing;
statistical analysis;
chip design;
wear out phenomena;
power supply voltage;
parametric delay variability;
leakage power variability;
statistical timing;
probabilistic paradigm;
8.
A formal software synthesis approach for embedded hard real-time systems
机译:
嵌入式硬实时系统的正式软件综合方法
作者:
Barreto R.
;
Neves M.
;
Oliveira M. Jr.
;
Maciel P.
;
Tavares E.
;
Lima R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
Petri nets;
embedded systems;
hardware-software codesign;
formal specification;
program compilers;
operating system kernels;
program verification;
processor scheduling;
formal software synthesis;
embedded hard real time systems;
software program;
general purpose language;
operating system kernels;
automatic software synthesis method;
code generation;
Petri nets;
compilers;
formal methods;
heated humidifier;
scheduling;
resource management;
synchronization;
specification model;
9.
Exception handling in microprocessors using assertion libraries
机译:
使用断言库处理微处理器的例外
作者:
Sica F.C.
;
Coelho C.N. Jr.
;
Nacif J.A.M.
;
Foster H.
;
Fernandes A.O.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
exception handling;
microprocessor chips;
integrated circuit design;
system-on-chip;
exception handling mechanisms;
microprocessor cores;
assertion libraries;
SoC design;
system-on-a-chip design;
assertion processor;
10.
Modeling and designing high performance analog reconfigurable circuits
机译:
建模和设计高性能模拟可重构电路
作者:
Fabris E.E.
;
Carro L.
;
Bampi S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
field programmable gate arrays;
integrated circuit design;
integrated circuit modelling;
system-on-chip;
field programmable analogue arrays;
mixed analogue-digital integrated circuits;
analog reconfigurable circuit design;
analog reconfigurable circuit modeling;
mixed signal front end interface;
SOC;
fixed analog cell;
high level design space exploration;
programmable analog processing functions;
digital modules;
FPGA platforms;
analog design automation;
11.
Test and design-for-test of mixed-signal integrated circuits
机译:
混合信号集成电路的测试和设计。
作者:
Huertas J.L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
design for testability;
integrated circuit design;
integrated circuit testing;
analogue integrated circuits;
digital integrated circuits;
built-in self test;
system-on-chip;
design for test;
mixed signal application specific integrated circuit;
complex signal application specific integrated circuit;
ASIC;
stimuli generation;
sufficient access;
single test output;
simple measurement set;
system level decomposition;
mixed signal function;
analog signal function;
integrated filters;
integrated analog-digital converters;
integrated digital-analog converters;
state of the art;
SoC;
systems-on-chip;
circuit testability;
fault coverage;
electronic system;
mixed signal test;
digital testing;
analog testing;
integrated circuit industry;
built-in self-test;
online test;
fault based testing;
specification based testing;
testing filters;
testing converters;
analog signal integrated circuits;
12.
A switch architecture and signal synchronization for GALS system-on-chips
机译:
用于GALS系统的交换机架构和信号同步
作者:
Zipf P.
;
Hinkelmann H.
;
Ashraf A.
;
Glesner M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
asynchronous circuits;
power consumption;
synchronisation;
integrated circuit design;
integrated circuit interconnections;
clocks;
VLSI;
circuit stability;
switch architecture;
signal synchronization;
globally asynchronous locally synchronous;
power consumption;
limiting factors;
chip-wide synchronous system-on-chip design;
asynchronous communication;
network-on-chips;
asynchronous method;
modular switch;
globally asynchronous interconnect network;
clock generators;
metastability;
VLSI;
13.
ATPG for fault diagnosis on analog electrical networks using evolutionary techniques
机译:
ATPG使用进化技术对模拟电气网络的故障诊断
作者:
Savioli C.E.F.
;
Szendrodi C.E.C.
;
Calvano J.V.
;
Mesquita A.C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automatic test pattern generation;
fault diagnosis;
genetic algorithms;
continuous time filters;
integrated circuit testing;
circuit optimisation;
mixed analogue-digital integrated circuits;
ATPG;
automated test pattern generation;
fault diagnosis;
continuous time analog electrical networks;
evolutionary techniques;
generic algorithm;
optimum frequencies;
parametric faults;
ad hoc features;
integrated circuit testing;
mixed analogue-digital integrated circuits;
14.
Statistical analysis and design: from picoseconds to probabilities
机译:
统计分析和设计:从PICOSECONDS到概率
作者:
Visweswariah C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
statistical analysis;
probability;
timing;
statistical analysis;
chip design;
wear out phenomena;
power supply voltage;
parametric delay variability;
leakage power variability;
statistical timing;
probabilistic paradigm;
15.
Design sequence for a LC-tank voltage controlled oscillator in CMOS for Rf
机译:
用于RF的CMOS中LC罐电压控制振荡器的设计序列
作者:
do Vale Neto J.V.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
voltage-controlled oscillators;
radiofrequency integrated circuits;
integrated circuit design;
CMOS integrated circuits;
LC tank voltage controlled oscillator;
RF integrated circuits;
VCO;
radio frequency integrated circuits;
active components;
transistors;
Austria micro systems;
CMOS fabrication technology;
2.4 to 2.5 GHz;
0.35 micron;
16.
An improved synthesis method for low power hardwired FIR filters
机译:
低功耗硬连线冷滤器的改进综合方法
作者:
Rosa V.S.
;
Costa E.
;
Monteiro J.C.
;
Bampi S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
low-power electronics;
FIR filters;
digital filters;
frequency response;
hardware description languages;
transfer functions;
low power hardwired FIR filters;
parallel digital finite impulse response filters;
fixed coefficients;
adders;
logic depth;
multiplier block;
n-power-of-two terms;
common subexpression elimination algorithm;
floating point coefficient set;
scale factor;
frequency response;
VHDL;
filter transfer characteristics;
low power design;
17.
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters
机译:
时钟偏斜器中的数字背景和盲校验在时间交错的模数转换器中的误差
作者:
Camarero D.
;
Naviner J.-F.
;
Loumeau P.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
analogue-digital conversion;
calibration;
nonlinear distortion;
adaptive filters;
FIR filters;
filtering theory;
clocks;
errors;
signal reconstruction;
digital circuits;
digital background;
blind calibration;
clock skew errors;
time interleaved analog-digital converters;
deterministic sample time errors;
time interleaved channels;
nonlinear distortion;
spurious free dynamic range;
fully digital calibration method;
adaptive FIR filters;
correctly sampled signal reconstruction;
blind clock skew detection algorithm;
parallel channels;
time interleaved architecture;
spurs attenuation;
signal to noise and distortion ratio;
18.
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
机译:
基于CAN协议的网络系统可靠性分析的多级方法
作者:
Corno F.
;
Acle J.P.
;
Reorda M.S.
;
Violante M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automotive electronics;
vehicle dynamics;
road safety;
controller area networks;
protocols;
traffic engineering computing;
multilevel approach;
dependability analysis;
networked systems;
CAN protocol;
safety critical applications;
digital components;
mechanical components;
automotive fields;
complex tasks;
functional models;
vehicle dynamics;
19.
ATPG for fault diagnosis on analog electrical networks using evolutionary techniques
机译:
ATPG使用进化技术对模拟电气网络的故障诊断
作者:
Savioli C.E.F.
;
Szendrodi C.E.C.
;
Calvano J.V.
;
Mesquita A.C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automatic test pattern generation;
fault diagnosis;
genetic algorithms;
continuous time filters;
integrated circuit testing;
circuit optimisation;
mixed analogue-digital integrated circuits;
ATPG;
automated test pattern generation;
fault diagnosis;
continuous time analog electrical networks;
evolutionary techniques;
generic algorithm;
optimum frequencies;
parametric faults;
ad hoc features;
integrated circuit testing;
mixed analogue-digital integrated circuits;
20.
Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications
机译:
嵌入式应用程序实时调度算法的功率和性能调整
作者:
Becker L.B.
;
Wehrmeister M.A.
;
Pereira C.E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
embedded systems;
processor scheduling;
power consumption;
timing;
real time task scheduling algorithms;
embedded applications;
power consumption;
embedded systems;
timing;
design space exploration methodology;
CPU frequency;
performance tuning;
21.
Architecture and CAD for FPGAs
机译:
FPGA的建筑和CAD
作者:
Hutton M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
high level synthesis;
field programmable gate arrays;
reconfigurable architectures;
CAD software;
FPGA device architecture;
CPLD architecture;
PLD architecture;
prototyping;
interface logic;
modem devices;
flip flops;
DSP processing;
embedded memory;
embedded processors;
input-output standards;
embedded tranceivers;
EDA companies;
high level design;
hardware design;
22.
Characterization of MOS transistor current mismatch
机译:
MOS晶体管电流失配的特征
作者:
Klimach H.
;
Arnaud A.
;
Schneider M.C.
;
Galup-Montoro C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
MOSFET;
doping profiles;
integrated circuit testing;
integrated circuit design;
CMOS integrated circuits;
integrated circuit modelling;
integrated circuit measurement;
semiconductor device models;
MOS transistor current mismatch;
electron device matching;
analog electronic circuits;
digital electronic circuits;
drain current matching;
CMOS test structures;
bias conditions;
carrier number fluctuation theory;
doping fluctuations;
linear region;
saturation region;
process parameters;
geometric parameters;
integrated circuit measurement;
semiconductor device models;
integrated circuit modelling;
23.
A switch architecture and signal synchronization for GALS system-on-chips
机译:
用于GALS系统的交换机架构和信号同步
作者:
Zipf P.
;
Hinkelmann H.
;
Ashraf A.
;
Glesner M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
asynchronous circuits;
power consumption;
synchronisation;
integrated circuit design;
integrated circuit interconnections;
clocks;
VLSI;
circuit stability;
switch architecture;
signal synchronization;
globally asynchronous locally synchronous;
power consumption;
limiting factors;
chip-wide synchronous system-on-chip design;
asynchronous communication;
network-on-chips;
asynchronous method;
modular switch;
globally asynchronous interconnect network;
clock generators;
metastability;
VLSI;
24.
Leakage power optimization in standard-cell designs
机译:
漏电功率优化在标准单元设计中
作者:
Macii E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
CMOS integrated circuits;
leakage currents;
power consumption;
electronic design automation;
optimisation;
leakage power consumption;
optimization;
standard cell design;
integrated circuit design;
nanometer CMOS transistors;
gate leakage current;
sub-threshold leakage current;
feature size scaling;
sleep transistor insertion;
industry standard row based layout;
design tool;
commercial EDA tool;
25.
A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability
机译:
1.8 V电源多频可用可调式片式IC振荡器,具有低压检测能力
作者:
Boas A.L.V.
;
Soldera J.B.D.
;
Olmos A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
oscillators;
system-on-chip;
isolation technology;
current mirrors;
CMOS integrated circuits;
timing jitter;
low-power electronics;
multifrequency onchip IC oscillator;
digitally trimmable onchip IC oscillator;
bandgap cell;
bandgap isolation method;
wide swing cascode current mirrors;
noise coupling reduction;
oscillator fine tuning;
clock jitter;
low voltage detection circuit;
SoC;
CMOS technology;
4 MHz;
8 MHz;
12 MHz;
22 MHz;
1.8 to 5.5 V;
-40 to 125 degC;
0.5 micron;
5 mus;
26.
Modeling and designing high performance analog reconfigurable circuits
机译:
建模和设计高性能模拟可重构电路
作者:
Fabris E.E.
;
Carro L.
;
Bampi S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
field programmable gate arrays;
integrated circuit design;
integrated circuit modelling;
system-on-chip;
field programmable analogue arrays;
mixed analogue-digital integrated circuits;
analog reconfigurable circuit design;
analog reconfigurable circuit modeling;
mixed signal front end interface;
SOC;
fixed analog cell;
high level design space exploration;
programmable analog processing functions;
digital modules;
FPGA platforms;
analog design automation;
27.
An automatic testbench generation tool for a systemC functional verification methodology
机译:
用于SystemC功能验证方法的自动测试禁止生成工具
作者:
da Silva K.R.G.
;
Melcher E.U.K.
;
Araujo G.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automatic testing;
formal verification;
integrated circuit design;
software libraries;
computational complexity;
system-on-chip;
VLSI;
electronic engineering computing;
automatic testbench generation tool;
systemC functional verification methodology;
VLSI technology;
SoC design;
electronic circuits;
automatic verification methodology;
transaction level;
coverage driven;
self checking;
random constraint functional verification;
systemC verification library;
MP3 design;
28.
A 0.8 /spl mu/m CMOS switched-capacitor video filter
机译:
0.8 / SPL MU / M CMOS开关电容视频滤波器
作者:
Petraglia A.
;
Canive J.M.
;
Petraglia M.R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
CMOS analogue integrated circuits;
switched capacitor filters;
low-pass filters;
elliptic filters;
integrated circuit testing;
integrated circuit design;
integrated circuit measurement;
all-pass filters;
CMOS switched capacitor video filter;
sensitivity;
switched capacitor filtering structures;
computer simulation;
fifth order low pass elliptic filter;
video frequency applications;
sampling frequency;
IC prototype;
standard double-poly CMOS process;
passband frequency deviation;
passband edge frequency;
all-pass filters;
analogue integrated circuits;
integrated circuit testing;
integrated circuit measurement;
0.8 micron;
16 MHz;
3.4 MHz;
29.
A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping
机译:
一种基于Systemc基于System应用程序应用程序应用程序应用虚拟原型模拟方法
作者:
Meise C.
;
Grimm C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
virtual prototyping;
rapid prototyping (industrial);
software tools;
C++ language;
analogue integrated circuits;
automotive electronics;
circuit simulation;
digital simulation;
real-time systems;
mixed analogue-digital integrated circuits;
SystemC;
sensor application;
BeCom modeling methodology;
behavioral component level simulator;
virtual prototyping;
rapid prototyping;
mixed signal systems;
automotive industry;
automotive tools;
MatrixX;
Simulink;
physical properties;
analog circuit models;
behavioral models;
real time simulation;
C++ language;
30.
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic
机译:
模型和原型动态可重构系统,用于通过重写逻辑有效计算动态规划方法
作者:
Ayala-Rincon M.
;
Jacobi R.P.
;
Carvalho L.G.A.
;
Llanos C.H.
;
Hartenstein R.W.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
rewriting systems;
systolic arrays;
reconfigurable architectures;
dynamic programming;
field programmable gate arrays;
hardware description languages;
computational complexity;
digital systems;
software prototyping;
modeling;
prototyping;
dynamically reconfigurable systems;
dynamic programming;
rewriting-logic environments;
reconfigurable systolic arrays;
computational problems;
reconfigurable systolic architectures;
digital systems;
global sequence alignment;
local sequence alignment;
Smith-Waterman algorithm;
approximate string matching;
longest common subsequence;
VHDL;
rewriting-logic based abstract models;
FPGA;
APEX family;
31.
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology
机译:
在0.35 / SPL MU / M CMOS技术中,4 GHz双模分压器-32/33预分频器
作者:
de Miranda F.P.H.
;
Navarro S.J. Jr.
;
Van Noije W.A.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
frequency dividers;
prescalers;
frequency synthesizers;
integrated circuit layout;
low-power electronics;
CMOS digital integrated circuits;
high-speed integrated circuits;
dual modulus divider;
32/33 prescaler;
CMOS technology;
high frequency synthesizer designs;
extended true single phase clock technique;
power consumption;
integrated circuit layout;
low-power electronics;
high speed integrated circuits;
4 GHz;
0.35 micron;
4.38 mW;
3.3 V;
32.
Non-Manhattan maze routing
机译:
非曼哈顿迷宫路线
作者:
Stan M.R.
;
Hamzaoglu F.
;
Garrett D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
network routing;
integrated circuits;
graph theory;
nonManhattan multilayer maze routing;
Manhattan multilayer maze routing;
multiple metal layers;
IC processes;
average interconnect length;
performance improvement;
routability improvement;
arbitrary number;
four layer routing;
nonManhattan algorithms;
graph theory;
33.
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
机译:
基于实时LUT的网络拓扑,用于动态和部分FPGA自我重新配置
作者:
Heubner M.
;
Becker T.
;
Becker J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
integrated logic circuits;
field programmable gate arrays;
network topology;
table lookup;
electronic engineering computing;
real time look up table;
network topology;
Xilinx XC2V3000 FPGA;
run time reconfiguration;
TBUF element;
routing tool;
automatic modular design flow;
34.
Reducing test time with processor reuse in network-on-chip based systems
机译:
在基于网络的网络系统中减少了处理器重用的测试时间
作者:
Amory A.M.
;
Cota E.
;
Lubaszewski M.
;
Moraes F.G.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
circuit analysis computing;
integrated circuit testing;
embedded systems;
processor reuse;
network-on-chip;
test planning method;
test sources;
system-on-chip;
power dissipation;
embedded processors;
circuit analysis computing;
35.
Design sequence for a LC-tank voltage controlled oscillator in CMOS for Rf
机译:
用于RF的CMOS中LC罐电压控制振荡器的设计序列
作者:
do Vale Neto J.V.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
voltage-controlled oscillators;
radiofrequency integrated circuits;
integrated circuit design;
CMOS integrated circuits;
LC tank voltage controlled oscillator;
RF integrated circuits;
VCO;
radio frequency integrated circuits;
active components;
transistors;
Austria micro systems;
CMOS fabrication technology;
2.4 to 2.5 GHz;
0.35 micron;
36.
Dual-mode RF receiver front-end using a 0.25-/spl mu/m 60-GHz f/sub T/ SiGe:C BiCMOS7RF technology
机译:
双模RF接收器前端使用0.25- / SPL MU / M 60-GHz F / SUM T / SIGE:C BICMOS7RF技术
作者:
Moreira C.P.
;
Kerherve E.
;
Jarry P.
;
Shirakawa A.A.
;
Belot D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
radio receivers;
radiofrequency integrated circuits;
BiCMOS integrated circuits;
radiofrequency amplifiers;
mixers (circuits);
convertors;
integrated circuit layout;
dual mode RF receiver front end;
LNA;
active single-ended-to-differential converter;
down conversion mixer;
BiCMOS7RF integration technology;
STMicroelectronics;
GSM1800 system;
WCDMA FDD systems;
parallel receiver chains;
integrated circuit layout;
18 mW;
2.5 V;
0.25 micron;
60 GHz;
2110 to 2170 MHz;
1805 to 1880 MHz;
SiGe:C;
37.
Design of RF CMOS low noise amplifiers using a current based MOSFET model
机译:
使用基于电流的MOSFET模型设计RF CMOS低噪声放大器的设计
作者:
Baroncini V.H.V.
;
da Costa Gouveia-Filho O.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
radiofrequency amplifiers;
radiofrequency integrated circuits;
CMOS integrated circuits;
MOSFET;
integrated circuit design;
integrated circuit noise;
semiconductor device noise;
semiconductor device models;
RF CMOS low noise amplifier design;
LNA;
current based MOSFET model;
MOSFET inversion regions;
induced gate noise;
MOS devices;
38.
When reconfigurable architecture meets network-on-chip
机译:
可重新配置架构符合片上网时
作者:
Soares R.
;
Silva I.S.
;
Azevedo A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
reconfigurable architectures;
parallel architectures;
system-on-chip;
microprocessor chips;
discrete cosine transforms;
integrated circuit design;
reconfigurable architecture;
network-on-chip;
communication subsystem;
parallel architecture;
SystemC;
NoCX4;
coarse grained reconfigurable microprocessor;
processing nodes;
load generator program;
2D-DCT coefficients;
router architecture;
39.
Low power gate-level design with mixed-V/sub th/ (MVT) techniques
机译:
低功率门级设计,具有混合V / SUB TH /(MVT)技术
作者:
Sill F.
;
Grassert F.
;
Timmermann D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
leakage currents;
logic gates;
CMOS logic circuits;
integrated circuit design;
mixed analogue-digital integrated circuits;
MOSFET;
low power gate level design;
mixed V/sub th/ CMOS design;
leakage power reduction;
multithreshold technique;
threshold voltage;
logic gate;
MOS transistor;
40.
Test and design-for-test of mixed-signal integrated circuits
机译:
混合信号集成电路的测试和设计。
作者:
Huertas J.L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
design for testability;
integrated circuit design;
integrated circuit testing;
analogue integrated circuits;
digital integrated circuits;
built-in self test;
system-on-chip;
design for test;
mixed signal application specific integrated circuit;
complex signal application specific integrated circuit;
ASIC;
stimuli generation;
sufficient access;
single test output;
simple measurement set;
system level decomposition;
mixed signal function;
analog signal function;
integrated filters;
integrated analog-digital converters;
integrated digital-analog converters;
state of the art;
SoC;
systems-on-chip;
circuit testability;
fault coverage;
electronic system;
mixed signal test;
digital testing;
analog testing;
integrated circuit industry;
built-in self-test;
online test;
fault based testing;
specification based testing;
testing filters;
testing converters;
analog signal integrated circuits;
41.
An improved synthesis method for low power hardwired FIR filters
机译:
低功耗硬连线冷滤器的改进综合方法
作者:
Rosa V.S.
;
Costa E.
;
Monteiro J.C.
;
Bampi S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
low-power electronics;
FIR filters;
digital filters;
frequency response;
hardware description languages;
transfer functions;
low power hardwired FIR filters;
parallel digital finite impulse response filters;
fixed coefficients;
adders;
logic depth;
multiplier block;
n-power-of-two terms;
common subexpression elimination algorithm;
floating point coefficient set;
scale factor;
frequency response;
VHDL;
filter transfer characteristics;
low power design;
42.
Body-bias compensation technique for subthreshold CMOS static logic gates
机译:
亚阈值CMOS静态逻辑门的身体偏置补偿技术
作者:
Melek L.A.P.
;
Schneider M.C.
;
Galup-Montoro C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
CMOS logic circuits;
compensation;
digital simulation;
logic gates;
MOSFET;
invertors;
body bias compensation technique;
subthreshold CMOS static logic gates;
CMOS inverter;
NAND-2 gate;
NOR-2 static logic gates;
PMOS transistors;
NMOS transistor;
computer simulations;
drain currents;
bias circuits;
BSIM3v3 model;
AMS technology;
AMIS technology;
0.8 micron;
1.5 micron;
0.35 micron;
43.
A VLIW low power Java processor for embedded applications
机译:
用于嵌入式应用程序的VLIW低功耗Java处理器
作者:
Beck A.C.S.
;
Carro L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
multiprocessing systems;
Java;
discrete cosine transforms;
embedded systems;
power consumption;
microcontrollers;
low-power electronics;
very long instruction word;
VLIW low power Java processor;
embedded applications;
stack architecture;
power dissipation;
memory access instruction;
cache accesses;
inverse modified DCT;
discrete cosine transform;
data processing benchmark;
microcontroller;
44.
A programmable cellular neural network circuit
机译:
可编程蜂窝神经网络电路
作者:
Leong M.
;
Vasconcelos P.
;
Fernandes J.R.
;
Sousa L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
cellular neural nets;
digital-analogue conversion;
integrated circuit testing;
integrated circuit layout;
circuit simulation;
SPICE;
programmable cellular neural network circuit;
DAC;
digital-analog converter;
Matlab;
Java;
CMOS technology;
cadence design framework;
Pspice/Spectre;
0.35 micron;
45.
Advanced technology mapping for standard-cell generators
机译:
标准单元发电机的高级技术映射
作者:
Correia V.
;
Reis A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
logic gates;
decision trees;
logic partitioning;
SPICE;
timing;
technology mapping;
standard cell generators;
AND/OR circuit decompositions;
n-ary tree representation;
circuit depth calculation;
logic gates;
area measurement;
transistor count;
SIS mapping;
libraries;
timing;
SPICE simulation;
46.
Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits
机译:
低功耗双v / sub / pseudo双v / sub dd / domino电路
作者:
Dhillon Y.S.
;
Diril A.U.
;
Chatterjee A.
;
Singh A.D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
high-speed integrated circuits;
CMOS logic circuits;
low-power electronics;
power consumption;
combinational circuits;
logic gates;
integrated circuit design;
domino circuits;
domino logic gates;
CMOS logic;
power consumption;
low power domino gate design;
combinational circuits;
circuit delay;
ISCAS 85 benchmark circuits;
circuit timing;
47.
Task scheduling for heterogeneous reconfigurable computers
机译:
异构可重新配置计算机的任务调度
作者:
Ahmadinia A.
;
Bobda C.
;
Koch D.
;
Majer M.
;
Teich J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
reconfigurable architectures;
processor scheduling;
operating systems (computers);
field programmable gate arrays;
electronic engineering computing;
task scheduling;
heterogeneous reconfigurable computers;
operating system;
reconfigurable device;
databases;
field programmable gate arrays;
48.
TheoSim: combining symbolic simulation and theorem proving for hardware verification
机译:
TheOSIM:结合符号仿真和定理证明硬件验证
作者:
Sammane G.A.
;
Schmaltz J.
;
Toma D.
;
Ostier P.
;
Borrione D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
theorem proving;
symbol manipulation;
hardware description languages;
formal verification;
digital integrated circuits;
digital systems;
system-on-chip;
integrated circuit design;
TheoSim;
symbolic simulation;
theorem proving;
hardware verification;
symbolic verification tool;
digital integrated systems;
network on chip architecture;
49.
Architecture and CAD for FPGAs
机译:
FPGA的建筑和CAD
作者:
Hutton M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
high level synthesis;
field programmable gate arrays;
reconfigurable architectures;
CAD software;
FPGA device architecture;
CPLD architecture;
PLD architecture;
prototyping;
interface logic;
modem devices;
flip flops;
DSP processing;
embedded memory;
embedded processors;
input-output standards;
embedded tranceivers;
EDA companies;
high level design;
hardware design;
50.
On the dynamic behavior of a novel digital-only sigma-delta A/D converter
机译:
关于一种新型Digital Indiply Sigma-Delta A / D转换器的动态行为
作者:
Jacomet M.
;
Goette J.
;
Zbinden V.
;
Narvaez C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
sigma-delta modulation;
field programmable gate arrays;
microcomputers;
dynamic behavior;
digital only sigma-delta A/D converter;
sigma-delta analog-digital converters;
analog modulator;
digital filter;
first order modulator;
active analog components;
FPGA;
microprocessor software;
51.
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology
机译:
在0.35 / SPL MU / M CMOS技术中,4 GHz双模分压器-32/33预分频器
作者:
de Miranda F.P.H.
;
Navarro S.J. Jr.
;
Van Noije W.A.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
frequency dividers;
prescalers;
frequency synthesizers;
integrated circuit layout;
low-power electronics;
CMOS digital integrated circuits;
high-speed integrated circuits;
dual modulus divider;
32/33 prescaler;
CMOS technology;
high frequency synthesizer designs;
extended true single phase clock technique;
power consumption;
integrated circuit layout;
low-power electronics;
high speed integrated circuits;
4 GHz;
0.35 micron;
4.38 mW;
3.3 V;
52.
A formal software synthesis approach for embedded hard real-time systems
机译:
嵌入式硬实时系统的正式软件综合方法
作者:
Barreto R.
;
Neves M.
;
Oliveira M. Jr.
;
Maciel P.
;
Tavares E.
;
Lima R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
Petri nets;
embedded systems;
hardware-software codesign;
formal specification;
program compilers;
operating system kernels;
program verification;
processor scheduling;
formal software synthesis;
embedded hard real time systems;
software program;
general purpose language;
operating system kernels;
automatic software synthesis method;
code generation;
Petri nets;
compilers;
formal methods;
heated humidifier;
scheduling;
resource management;
synchronization;
specification model;
53.
Leakage power optimization in standard-cell designs
机译:
漏电功率优化在标准单元设计中
作者:
Macii E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
CMOS integrated circuits;
leakage currents;
power consumption;
electronic design automation;
optimisation;
leakage power consumption;
optimization;
standard cell design;
integrated circuit design;
nanometer CMOS transistors;
gate leakage current;
sub-threshold leakage current;
feature size scaling;
sleep transistor insertion;
industry standard row based layout;
design tool;
commercial EDA tool;
54.
Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications
机译:
嵌入式应用程序实时调度算法的功率和性能调整
作者:
Becker L.B.
;
Wehrmeister M.A.
;
Pereira C.E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
embedded systems;
processor scheduling;
power consumption;
timing;
real time task scheduling algorithms;
embedded applications;
power consumption;
embedded systems;
timing;
design space exploration methodology;
CPU frequency;
performance tuning;
55.
Non-Manhattan maze routing
机译:
非曼哈顿迷宫路线
作者:
Stan M.R.
;
Hamzaoglu F.
;
Garrett D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
network routing;
integrated circuits;
graph theory;
nonManhattan multilayer maze routing;
Manhattan multilayer maze routing;
multiple metal layers;
IC processes;
average interconnect length;
performance improvement;
routability improvement;
arbitrary number;
four layer routing;
nonManhattan algorithms;
graph theory;
56.
Characterization of MOS transistor current mismatch
机译:
MOS晶体管电流失配的特征
作者:
Klimach H.
;
Arnaud A.
;
Schneider M.C.
;
Galup-Montoro C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
MOSFET;
doping profiles;
integrated circuit testing;
integrated circuit design;
CMOS integrated circuits;
integrated circuit modelling;
integrated circuit measurement;
semiconductor device models;
MOS transistor current mismatch;
electron device matching;
analog electronic circuits;
digital electronic circuits;
drain current matching;
CMOS test structures;
bias conditions;
carrier number fluctuation theory;
doping fluctuations;
linear region;
saturation region;
process parameters;
geometric parameters;
integrated circuit measurement;
semiconductor device models;
integrated circuit modelling;
57.
Low power gate-level design with mixed-V/sub th/ (MVT) techniques
机译:
低功率门级设计,具有混合V / SUB TH /(MVT)技术
作者:
Sill F.
;
Grassert F.
;
Timmermann D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
leakage currents;
logic gates;
CMOS logic circuits;
integrated circuit design;
mixed analogue-digital integrated circuits;
MOSFET;
low power gate level design;
mixed V/sub th/ CMOS design;
leakage power reduction;
multithreshold technique;
threshold voltage;
logic gate;
MOS transistor;
58.
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
机译:
混合信号CMOS IC中粘接与包装串扰计算机仿真方法
作者:
Trucco G.
;
Boselli G.
;
Liberali V.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
crosstalk;
digital simulation;
analogue simulation;
circuit simulation;
CMOS logic circuits;
circuit switching;
integrated circuit bonding;
mixed analogue-digital integrated circuits;
time-domain analysis;
SPICE;
integrated circuit packaging;
computer simulation;
bonding wires;
package crosstalk;
mixed signal CMOS IC;
circuit simulation;
crosstalk effect estimation;
CMOS logic gate;
digital switching noise;
time domain;
computer program;
analog simulation;
SPICE;
mixed analog-digital CMOS integrated circuit;
59.
Improving mixed-single SOC testing: a power-aware reuse-based approach with analog BIST
机译:
改善混合单SoC测试:基于动力感知的重用基于模拟BIST的方法
作者:
Andrade A. Jr.
;
Cota E.
;
Lubaszewski M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
built-in self test;
system-on-chip;
mixed analogue-digital integrated circuits;
integrated circuit testing;
mixed signal SoC testing;
power aware reuse based approach;
analog BIST;
cost effective test solution;
global system testing time;
digital blocks;
analog signals testing;
60.
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
机译:
在电感耦合的片上互连中准确捕获定时参数
作者:
Murugan T.
;
Schlachta C.
;
Petrov M.
;
Indrusiak L.
;
Garcia A.
;
Glesner M.
;
Reis R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
coupled circuits;
crosstalk;
timing;
delays;
integrated circuit interconnections;
system-on-chip;
inductance;
integrated circuit modelling;
timing parameter capture;
on-chip frequency;
signal rise time;
timing analysis;
high frequency on-chip interconnects;
inductive coupling;
crosstalk;
signal fall time;
data toggling pattern.;
switching patterns;
61.
A multi-standard channel-decoder for base-station applications
机译:
基站应用程序的多标准通道解码器
作者:
Vogt T.
;
Wehn N.
;
Alves P.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
convolutional codes;
VLSI;
code division multiple access;
decoding;
maximum likelihood estimation;
channel coding;
multistandard channel decoder;
base station applications;
VLSI;
enchanced data rate;
global evolution;
WCDMA;
convolutional codes;
convolutional decoding;
MAP algorithm;
clock frequency;
200 MHz;
62.
A fully integrated physical activity sensing circuit for implantable pacemakers
机译:
用于植入起搏器的全集成物理活性传感电路
作者:
Arnaud A.
;
Galup-Montoro C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
band-pass filters;
amplifiers;
pacemakers;
CMOS integrated circuits;
low-power electronics;
accelerometers;
piezoelectric transducers;
medical signal processing;
analogue integrated circuits;
integrated circuit design;
integrated physical activity sensing circuit;
implantable pacemakers;
bandpass filter amplifier;
piezoelectric accelerometer;
rate adaptive pacemaker;
analogue integrated circuit;
CMOS;
signal conditioning;
2 V;
230 nA;
63.
On the dynamic behavior of a novel digital-only sigma-delta A/D converter
机译:
关于一种新型Digital Indiply Sigma-Delta A / D转换器的动态行为
作者:
Jacomet M.
;
Goette J.
;
Zbinden V.
;
Narvaez C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
sigma-delta modulation;
field programmable gate arrays;
microcomputers;
dynamic behavior;
digital only sigma-delta A/D converter;
sigma-delta analog-digital converters;
analog modulator;
digital filter;
first order modulator;
active analog components;
FPGA;
microprocessor software;
64.
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
机译:
混合信号CMOS IC中粘接与包装串扰计算机仿真方法
作者:
Trucco G.
;
Boselli G.
;
Liberali V.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
crosstalk;
digital simulation;
analogue simulation;
circuit simulation;
CMOS logic circuits;
circuit switching;
integrated circuit bonding;
mixed analogue-digital integrated circuits;
time-domain analysis;
SPICE;
integrated circuit packaging;
computer simulation;
bonding wires;
package crosstalk;
mixed signal CMOS IC;
circuit simulation;
crosstalk effect estimation;
CMOS logic gate;
digital switching noise;
time domain;
computer program;
analog simulation;
SPICE;
mixed analog-digital CMOS integrated circuit;
65.
ParIS: a parameterizable interconnect switch for networks-on-chip
机译:
巴黎:用于片上网络的可参数化互连开关
作者:
Zeferino C.A.
;
Santo F.G.M.E.
;
Susin A.A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
multiprocessor interconnection networks;
network routing;
parallel architectures;
hardware description languages;
ParIS;
parameterizable interconnect switch;
networks-on-chip;
interconnecting cores;
systems-on-chip;
SoC;
reusable communication architecture;
scalable communication architecture;
parameterizable router architecture;
router configuration;
performance requirements;
hardware description languages;
66.
Task scheduling for heterogeneous reconfigurable computers
机译:
异构可重新配置计算机的任务调度
作者:
Ahmadinia A.
;
Bobda C.
;
Koch D.
;
Majer M.
;
Teich J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
reconfigurable architectures;
processor scheduling;
operating systems (computers);
field programmable gate arrays;
electronic engineering computing;
task scheduling;
heterogeneous reconfigurable computers;
operating system;
reconfigurable device;
databases;
field programmable gate arrays;
67.
Advances and trends in FPGA design
机译:
FPGA设计的进展和趋势
作者:
Hutton M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
field programmable gate arrays;
application specific integrated circuits;
integrated circuit design;
programmable logic devices;
FPGA design;
embedded tranceiver;
structured ASIC;
CPLD applications;
68.
A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping
机译:
一种基于Systemc基于System应用程序应用程序应用程序应用虚拟原型模拟方法
作者:
Meise C.
;
Grimm C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
virtual prototyping;
rapid prototyping (industrial);
software tools;
C++ language;
analogue integrated circuits;
automotive electronics;
circuit simulation;
digital simulation;
real-time systems;
mixed analogue-digital integrated circuits;
SystemC;
sensor application;
BeCom modeling methodology;
behavioral component level simulator;
virtual prototyping;
rapid prototyping;
mixed signal systems;
automotive industry;
automotive tools;
MatrixX;
Simulink;
physical properties;
analog circuit models;
behavioral models;
real time simulation;
C++ language;
69.
Avionic systems overview
机译:
航空系统概述
作者:
Carbonari A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
avionics;
aircraft;
aerospace computing;
aviation electronics;
electrical systems;
electronic system;
computers;
sensors;
actuators;
control units;
display units;
reliability;
avionic systems architectures;
civil aircraft;
military aircraft;
70.
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
机译:
基于CAN协议的网络系统可靠性分析的多级方法
作者:
Corno F.
;
Acle J.P.
;
Reorda M.S.
;
Violante M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automotive electronics;
vehicle dynamics;
road safety;
controller area networks;
protocols;
traffic engineering computing;
multilevel approach;
dependability analysis;
networked systems;
CAN protocol;
safety critical applications;
digital components;
mechanical components;
automotive fields;
complex tasks;
functional models;
vehicle dynamics;
71.
An automatic testbench generation tool for a systemC functional verification methodology
机译:
用于SystemC功能验证方法的自动测试禁止生成工具
作者:
da Silva K.R.G.
;
Melcher E.U.K.
;
Araujo G.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
automatic testing;
formal verification;
integrated circuit design;
software libraries;
computational complexity;
system-on-chip;
VLSI;
electronic engineering computing;
automatic testbench generation tool;
systemC functional verification methodology;
VLSI technology;
SoC design;
electronic circuits;
automatic verification methodology;
transaction level;
coverage driven;
self checking;
random constraint functional verification;
systemC verification library;
MP3 design;
72.
FPGA implementation of parallel turbo-decoders
机译:
FPGA的并行涡轮解码器的实施
作者:
Thul M.J.
;
Wehn N.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
turbo codes;
decoding;
field programmable gate arrays;
maximum likelihood decoding;
maximum likelihood estimation;
forward error correction;
error correction codes;
parallel architectures;
reliability theory;
FPGA;
parallel turbo decoders;
wireless communication;
turbo codes;
forward error correction;
data transfer reliability;
nonrecurring engineering;
turbo decoder architecture;
low volume devices;
system throughput;
Xilinx Virtex-II family;
Virtex-II 3000;
latency time;
maximum likelihood estimation;
26 Mbit/s;
84 MHz;
185 mus;
73.
RTL power estimation and optimization
机译:
RTL功率估计和优化
作者:
Macii E.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
electronic design automation;
power consumption;
optimisation;
integrated circuit design;
circuit CAD;
RTL power estimation;
power optimization;
power consumption;
electronic systems;
mobile telecom;
desktop computers;
portable computers;
nanometer technology;
ambient intelligence;
sensor networks;
design process;
state of the art techniques;
data path macros;
steering logic;
memory hierarchy;
bus interface synthesis;
clock gating strategy;
clock tree planning;
CAD tools;
EDA market;
74.
Advanced technology mapping for standard-cell generators
机译:
标准单元发电机的高级技术映射
作者:
Correia V.
;
Reis A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
logic gates;
decision trees;
logic partitioning;
SPICE;
timing;
technology mapping;
standard cell generators;
AND/OR circuit decompositions;
n-ary tree representation;
circuit depth calculation;
logic gates;
area measurement;
transistor count;
SIS mapping;
libraries;
timing;
SPICE simulation;
75.
When reconfigurable architecture meets network-on-chip
机译:
可重新配置架构符合片上网时
作者:
Soares R.
;
Silva I.S.
;
Azevedo A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
reconfigurable architectures;
parallel architectures;
system-on-chip;
microprocessor chips;
discrete cosine transforms;
integrated circuit design;
reconfigurable architecture;
network-on-chip;
communication subsystem;
parallel architecture;
SystemC;
NoCX4;
coarse grained reconfigurable microprocessor;
processing nodes;
load generator program;
2D-DCT coefficients;
router architecture;
76.
ParIS: a parameterizable interconnect switch for networks-on-chip
机译:
巴黎:用于片上网络的可参数化互连开关
作者:
Zeferino C.A.
;
Santo F.G.M.E.
;
Susin A.A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
multiprocessor interconnection networks;
network routing;
parallel architectures;
hardware description languages;
ParIS;
parameterizable interconnect switch;
networks-on-chip;
interconnecting cores;
systems-on-chip;
SoC;
reusable communication architecture;
scalable communication architecture;
parameterizable router architecture;
router configuration;
performance requirements;
hardware description languages;
77.
A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS
机译:
低功耗13-GB / s 2 / SUP 7 / -1伪随机位序列发生器IC,120 nm散装CMOS
作者:
Wohlmuth H.-D.
;
Kehrer D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
random sequences;
CMOS integrated circuits;
shift registers;
binary sequences;
logic gates;
integrated circuit design;
low-power electronics;
circuit feedback;
trigger circuits;
power consumption;
frequency dividers;
low power electronics;
pseudo random bit sequence generator IC;
bulk CMOS technology;
7 bit full rate shift register;
linear XOR feedback;
data rates;
trigger divider;
3 bit shifted outputs;
autostart logic;
13 Kbyte/s;
137 mA;
1.5 V;
120 nm;
78.
Accurate software performance estimation using domain classification and neural networks
机译:
使用域分类和神经网络准确的软件性能估算
作者:
Oyamada M.S.
;
Zschornack F.
;
Wanger F.R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
neural nets;
embedded systems;
software performance evaluation;
flow graphs;
parallel architectures;
topology;
accurate software performance estimation;
domain classification;
neural networks;
embedded system;
power consumption;
embedded software;
design space exploration;
branch prediction mechanism;
deep pipelines;
high level performance estimation;
automatic classification;
topological information extraction;
control flow graph;
79.
Body-bias compensation technique for subthreshold CMOS static logic gates
机译:
亚阈值CMOS静态逻辑门的身体偏置补偿技术
作者:
Melek L.A.P.
;
Schneider M.C.
;
Galup-Montoro C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
CMOS logic circuits;
compensation;
digital simulation;
logic gates;
MOSFET;
invertors;
body bias compensation technique;
subthreshold CMOS static logic gates;
CMOS inverter;
NAND-2 gate;
NOR-2 static logic gates;
PMOS transistors;
NMOS transistor;
computer simulations;
drain currents;
bias circuits;
BSIM3v3 model;
AMS technology;
AMIS technology;
0.8 micron;
1.5 micron;
0.35 micron;
80.
Verification and test challenges in SoC designs
机译:
SoC设计中的验证和测试挑战
作者:
Duenas C.A.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit testing;
SoC design;
system on chip;
functional verification;
IP block;
complex peripherals;
analog functions;
embedded memory;
81.
A VLIW low power Java processor for embedded applications
机译:
用于嵌入式应用程序的VLIW低功耗Java处理器
作者:
Beck A.C.S.
;
Carro L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
multiprocessing systems;
Java;
discrete cosine transforms;
embedded systems;
power consumption;
microcontrollers;
low-power electronics;
very long instruction word;
VLIW low power Java processor;
embedded applications;
stack architecture;
power dissipation;
memory access instruction;
cache accesses;
inverse modified DCT;
discrete cosine transform;
data processing benchmark;
microcontroller;
82.
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
机译:
在电感耦合的片上互连中准确捕获定时参数
作者:
Murugan T.
;
Schlachta C.
;
Petrov M.
;
Indrusiak L.
;
Garcia A.
;
Glesner M.
;
Reis R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
coupled circuits;
crosstalk;
timing;
delays;
integrated circuit interconnections;
system-on-chip;
inductance;
integrated circuit modelling;
timing parameter capture;
on-chip frequency;
signal rise time;
timing analysis;
high frequency on-chip interconnects;
inductive coupling;
crosstalk;
signal fall time;
data toggling pattern.;
switching patterns;
83.
Exception handling in microprocessors using assertion libraries
机译:
使用断言库处理微处理器的例外
作者:
Sica F.C.
;
Coelho C.N. Jr.
;
Nacif J.A.M.
;
Foster H.
;
Fernandes A.O.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
exception handling;
microprocessor chips;
integrated circuit design;
system-on-chip;
exception handling mechanisms;
microprocessor cores;
assertion libraries;
SoC design;
system-on-a-chip design;
assertion processor;
84.
Issues in parallelizing multigrid-based substrate model extraction and analysis
机译:
并行化多基于基于多基体的基于基于基于基于基于模型的提取和分析的问题
作者:
Silva J.M.S.
;
Silveria L.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
circuit complexity;
differential equations;
grid computing;
circuit simulation;
coupled circuits;
parallel processing;
substrates;
integrated circuit modelling;
multigrid based substrate model extraction;
substrate model analysis;
coupling effect;
mixed signal systems;
fast switching digital blocks;
high precision sensible analog circuitry;
miniaturization effect;
IC complexity;
distributed computing;
parallelization;
generic computations;
substrate coupling simulation;
85.
Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic
机译:
使用多个输出允许禁用CMOS差分逻辑增强32位携带展示前瞻加法器
作者:
Osorio M.C.B.
;
Sampaio C.A.
;
Reis A.I.
;
Ribas R.P.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
adders;
CMOS logic circuits;
SPICE;
circuit simulation;
enchanced carry look ahead adder;
multiple output enable-disable CMOS differential logic;
iterative networks;
self timed circuits;
recursive properties;
electrical simulation;
0.5 micron;
32 bit;
86.
Reducing test time with processor reuse in network-on-chip based systems
机译:
在基于网络的网络系统中减少了处理器重用的测试时间
作者:
Amory A.M.
;
Cota E.
;
Lubaszewski M.
;
Moraes F.G.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
circuit analysis computing;
integrated circuit testing;
embedded systems;
processor reuse;
network-on-chip;
test planning method;
test sources;
system-on-chip;
power dissipation;
embedded processors;
circuit analysis computing;
87.
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures
机译:
基于Adaptive DMA的I / O接口,用于多层可重新配置硬件架构中的数据流处理
作者:
Thomas A.
;
Zander T.
;
Becker J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
file organisation;
reconfigurable architectures;
data handling;
adaptive DMA based I/O interface;
direct memory access;
data stream handling;
multigrained reconfigurable hardware architectures;
multimedia communication;
mobile communication;
data processing architecture;
DSP;
microprocessor;
reconfigurable array architectures;
system controller;
88.
A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability
机译:
1.8 V电源多频可用可调式片式IC振荡器,具有低压检测能力
作者:
Boas A.L.V.
;
Soldera J.B.D.
;
Olmos A.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
oscillators;
system-on-chip;
isolation technology;
current mirrors;
CMOS integrated circuits;
timing jitter;
low-power electronics;
multifrequency onchip IC oscillator;
digitally trimmable onchip IC oscillator;
bandgap cell;
bandgap isolation method;
wide swing cascode current mirrors;
noise coupling reduction;
oscillator fine tuning;
clock jitter;
low voltage detection circuit;
SoC;
CMOS technology;
4 MHz;
8 MHz;
12 MHz;
22 MHz;
1.8 to 5.5 V;
-40 to 125 degC;
0.5 micron;
5 mus;
89.
Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic
机译:
使用多个输出允许禁用CMOS差分逻辑增强32位携带展示前瞻加法器
作者:
Osorio M.C.B.
;
Sampaio C.A.
;
Reis A.I.
;
Ribas R.P.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
adders;
CMOS logic circuits;
SPICE;
circuit simulation;
enchanced carry look ahead adder;
multiple output enable-disable CMOS differential logic;
iterative networks;
self timed circuits;
recursive properties;
electrical simulation;
0.5 micron;
32 bit;
90.
A partial reconfigurable architecture for controllers based on Petri nets
机译:
基于Petri网的控制器的部分可重新配置架构
作者:
Nascimento P.S.B.
;
Maciel P.R.M.
;
Lima M.E.
;
Santana R.E.
;
Filho A.G.S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
Petri nets;
digital control;
reconfigurable architectures;
programmable controllers;
field programmable gate arrays;
electronic engineering computing;
partial reconfigurable architecture;
Petri nets;
digital control system;
programmable logical controller;
operation cycle;
reconfigurable logic controller;
Xilinx Virtex-II FPGA architecture;
virtual hardware machine;
formal language;
sequential function chart;
91.
Will the ASIC survive?
机译:
AsiC会生存吗?
作者:
Camposano R.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
integrated circuit design;
application specific integrated circuits;
electronic design automation;
field programmable gate arrays;
ASIC design;
design cost;
ASSP;
semiconductor market;
standard cell based design;
EDA tools;
FPGA;
processor arrays;
92.
Distributed arithmetic FPGA design with online scalable size and performance
机译:
分布式算术FPGA设计,具有在线可扩展尺寸和性能
作者:
Danne K.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
distributed arithmetic;
field programmable gate arrays;
multiprogramming;
reconfigurable architectures;
integrated circuit design;
online scalable distributed arithmetic design;
FPGA design;
field programmable gate array;
partial runtime reconfiguration;
task execution;
multitasking;
93.
An ultra-low-power self-biased current reference
机译:
超低功耗自偏置电流参考
作者:
Camacho-Galeano E.M.
;
Galup-Montoro C.
;
Schneider M.C.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
low-power electronics;
CMOS integrated circuits;
MOSFET;
power consumption;
integrated circuit design;
network topology;
circuit simulation;
ultra low power self-biased current source;
AMIS CMOS technology;
power consumption;
MOSFET;
topology;
circuit simulation;
0.35 micron;
1.2 V;
1.1 V;
400 PA;
1.5 micron;
94.
Verification and test challenges in SoC designs
机译:
SoC设计中的验证和测试挑战
作者:
Duenas C.A.M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit testing;
SoC design;
system on chip;
functional verification;
IP block;
complex peripherals;
analog functions;
embedded memory;
95.
A partial reconfigurable architecture for controllers based on Petri nets
机译:
基于Petri网的控制器的部分可重新配置架构
作者:
Nascimento P.S.B.
;
Maciel P.R.M.
;
Lima M.E.
;
Santana R.E.
;
Filho A.G.S.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
Petri nets;
digital control;
reconfigurable architectures;
programmable controllers;
field programmable gate arrays;
electronic engineering computing;
partial reconfigurable architecture;
Petri nets;
digital control system;
programmable logical controller;
operation cycle;
reconfigurable logic controller;
Xilinx Virtex-II FPGA architecture;
virtual hardware machine;
formal language;
sequential function chart;
96.
Distributed arithmetic FPGA design with online scalable size and performance
机译:
分布式算术FPGA设计,具有在线可扩展尺寸和性能
作者:
Danne K.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
distributed arithmetic;
field programmable gate arrays;
multiprogramming;
reconfigurable architectures;
integrated circuit design;
online scalable distributed arithmetic design;
FPGA design;
field programmable gate array;
partial runtime reconfiguration;
task execution;
multitasking;
97.
A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS
机译:
低功耗13-GB / s 2 / SUP 7 / -1伪随机位序列发生器IC,120 nm散装CMOS
作者:
Wohlmuth H.-D.
;
Kehrer D.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
random sequences;
CMOS integrated circuits;
shift registers;
binary sequences;
logic gates;
integrated circuit design;
low-power electronics;
circuit feedback;
trigger circuits;
power consumption;
frequency dividers;
low power electronics;
pseudo random bit sequence generator IC;
bulk CMOS technology;
7 bit full rate shift register;
linear XOR feedback;
data rates;
trigger divider;
3 bit shifted outputs;
autostart logic;
13 Kbyte/s;
137 mA;
1.5 V;
120 nm;
98.
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures
机译:
基于Adaptive DMA的I / O接口,用于多层可重新配置硬件架构中的数据流处理
作者:
Thomas A.
;
Zander T.
;
Becker J.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
file organisation;
reconfigurable architectures;
data handling;
adaptive DMA based I/O interface;
direct memory access;
data stream handling;
multigrained reconfigurable hardware architectures;
multimedia communication;
mobile communication;
data processing architecture;
DSP;
microprocessor;
reconfigurable array architectures;
system controller;
99.
A programmable cellular neural network circuit
机译:
可编程蜂窝神经网络电路
作者:
Leong M.
;
Vasconcelos P.
;
Fernandes J.R.
;
Sousa L.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
cellular neural nets;
digital-analogue conversion;
integrated circuit testing;
integrated circuit layout;
circuit simulation;
SPICE;
programmable cellular neural network circuit;
DAC;
digital-analog converter;
Matlab;
Java;
CMOS technology;
cadence design framework;
Pspice/Spectre;
0.35 micron;
100.
Advances and trends in FPGA design
机译:
FPGA设计的进展和趋势
作者:
Hutton M.
会议名称:
《Symposium on Integrated Circuits and Systems Design》
|
2004年
关键词:
field programmable gate arrays;
application specific integrated circuits;
integrated circuit design;
programmable logic devices;
FPGA design;
embedded tranceiver;
structured ASIC;
CPLD applications;
意见反馈
回到顶部
回到首页