首页>外文会议>其他>IEEE symposium on high-performance computer architecture

IEEE symposium on high-performance computer architecture

召开年：
召开地：
出版时间：-

会议文集：-

会议论文

热门论文

全部论文

全选（0）

1.Fast barrier synchronization in wormhole k-ary n-cube networks with multidestination worms

机译：沃尔霍尔K-ARY N-CUBE网络的快速屏障同步与多程度蠕虫
- 作者：Panda D.K.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
2.Non-consistent dual register files to reduce register pressure

机译：非一致的双寄存器文件以减少寄存器压力
- 作者：Llosa J.;Valero M.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
3.Toward high communication performance through compiled communications on a circuit switched interconnection network

机译：通过在电路交换互连网络上编译通信来实现高通信性能
- 作者：Cappello F.;Germain C.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
4.Modeling virtual channel flow control in hypercubes

机译：超机中建模虚拟频道流量控制
- 作者：Boura Y.M.;Das C.R.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
5.Massively parallel array processor for logic, fault, and design error simulation

机译：用于逻辑，故障和设计错误仿真的大规模平行阵列处理器
- 作者：Hur Y.;Szygenda S.A.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
6.Simulation study of cached RAID5 designs

机译：缓存RAID5设计的仿真研究
- 作者：Treiber R.;Menon J.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
7.DASC cache

机译：DASC Cache.
- 作者：Seznec A.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
8.Software assistance for data caches

机译：数据缓存的软件帮助
- 作者：Temam O.;Drach N.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
9.A design framework for hybrid-access caches

机译：混合访问缓存的设计框架
- 作者：Theobald K.B.;Hum H.H.J.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
10.Fault-tolerant adaptive routing for two-dimensional meshes

机译：用于二维网格的容错自适应路由
- 作者：Cunningham C.M.;Avresky D.R.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
11.Architectural support for inter-stream communication in a MSIMD system

机译：MSIMD系统中流间通信的架构支持
- 作者：Garg V.;Schimmel D.E.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
12.Access ordering and memory-conscious cache utilization

机译：访问订购和内存有意识的缓存利用
- 作者：Mckee S.A.;Wulf W.A.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
13.Design and performance evaluation of a multithreaded architecture

机译：多线程架构的设计与绩效评估
- 作者：Govindarajan R.;Nemawarkar S.S.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
14.Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors

机译：基于硬件的跨度和共享内存多处理器中顺序预取的有效性
- 作者：Dahlgren F.;Stenstrom P.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
15.How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?

机译：在多个问题处理器中有多么有用的是非阻塞负载，流缓冲区和推测性执行？
- 作者：Farkas K.I.;Jouppi N.P.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
16.An initial evaluation of the Convex SPP-1000 for earth and space science applications

机译：地球和空间科学应用凸面SPP-1000的初步评估
- 作者：Sterling T.L.;Savarese D.F.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
17.An argument for simple COMA

机译：简单昏迷的论点
- 作者：Saulsbury A.;Wilkinson T.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
18.Abstracting network characteristics and locality properties of parallel systems

机译：摘要并行系统的网络特征和地区特性
- 作者：Sivasubramaniam A.;Singla M.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
19.Thread prioritization: a thread scheduling mechanism for multiple-context parallel processors

机译：线程优先级：多上下文并行处理器的线程调度机制
- 作者：Fiske S.;Dally W.J.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
20.U-cache: a cost-effective solution to synonym problem

机译：U-Cache：成本有效的同义词问题解决方案
- 作者：Jesung Kim;Sang Lyul Min;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
21.Program balance and its impact on high performance RISC architectures

机译：计划平衡及其对高性能RISC架构的影响
- 作者：John L.K.;Reddy V.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
22.Optimizing instruction cache performance for operating system intensive workloads

机译：优化操作系统密集型工作负载的指令缓存性能
- 作者：Torrellas J.;Chun Xia;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
23.Reducing communication latency with path multiplexing: in optically interconnected multiprocessor systems

机译：通过路径复用降低通信延迟：在光学互连的多处理器系统中
- 作者：Chunming Qiao;Melhem R.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
24.Efficient and balanced adaptive routing in two-dimensional meshes

机译：高效和平衡的自适应路由在二维网格中
- 作者：Upadhyay J.H.;Varavithya V.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
25.Implementing register interlocks in parallel-pipeline, multiple instruction queue, superscalar processors

机译：在并行管道中实现寄存器互锁，多个指令队列，超标卡处理器
- 作者：Weiss S.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
26.Fine-grain multi-thread processor architecture for massively parallel processing

机译：用于大规模并行处理的细粒度多线处理器架构
- 作者：Kawano T.;Kusakabe S.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
27.Creating a wider bus using caching techniques

机译：使用缓存技术创建更广泛的总线
- 作者：Citron D.;Rudolph L.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
28.A VLSI architecture for computing the tree-to-tree distance

机译：用于计算树到树距离的VLSI架构
- 作者：Sastry R.;Ranganathan N.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
29.Improving performance by cache driven memory management

机译：通过缓存驱动内存管理提高性能
- 作者：Westerholz K.;Honal S.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
30.The effects of STEF in finely parallel multithreaded processors

机译：Stef在细平平行多线程处理器中的影响
- 作者：Yamin Li;Wanming Chu;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
31.Implementation of atomic primitives on distributed shared memory multiprocessors

机译：分布式共享内存多处理器上的原始原语的实现
- 作者：Michael M.M.;Scott M.L.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
32.Software cache coherence for large scale multiprocessors

机译：大型多处理器的软件缓存一致性
- 作者：Kontothanassis L.I.;Scott M.L.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
33.Memory access reordering in vector processors

机译：在向量处理器中重新排序的内存访问
- 作者：De-Lei Lee;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
34.Two techniques for improving performance on bus-based multiprocessors

机译：用于提高基于总线的多处理器性能的两种技术
- 作者：Anderson C.;Baer J.-L.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
35.The Named-State Register File: implementation and performance

机译：命名状态寄存器文件：实现和性能
- 作者：Nuth P.R.;Dally W.J.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
36.Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture

机译：1995年第1届IEEE研讨会高性能计算机架构
- 作者：Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年
37.Origin-based fault-tolerant routing in the mesh

机译：基于原始的容错路由在网格中
- 作者：Libeskind-Hadas R.;Brandt E.;Institute of Electric and Electronic Engineer
- 会议名称：《IEEE symposium on high-performance computer architecture》 | 1995年