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Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems

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1.Register and Instruction Coverage Analysis for Different RISC-V ISA Modules

机译：用于不同RISC-V ISA模块的注册和指令覆盖分析
- 作者：Peer Adelt;Bastian Koppelmann;Wolfgang Mueller;Christoph Scheytt
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
2.APPEL - AGILA ProPErty and Dependency Description Language

机译：appel - agila属性和依赖描述语言
- 作者：Christoph Grimm;Frank Wawrzik;Alexander Louis-Ferdinand Jung;Konstantin Luebeck;Sebastian Post;Johannes Koch;Oliver Bringmann
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
3.Extending Verilator to Enable Fault Simulation

机译：扩展Verilator以启用故障模拟
- 作者：Endri Kaja;Nicolas Ojeda Leon;Michael Werner;Bogdan Andrei-Tabacaru;Keerthikumara Devarajegowda;Wolfgang Ecker
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
4.On Self-Verifying DSL Generation for Embedded Systems Automation

机译：嵌入式系统自动化自验证DSL生成
- 作者：Zhao Han;Shahzaib Qazi;Michael Werner;Keerthikumara Devarajegowda;Wolfgang Ecker
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
5.Benchmarking SMT Solvers on Automotive Code

机译：在汽车代码上基准标记SMT求解器
- 作者：Lukas Mentel;Karsten Scheibler;Felix Winterer;Bernd Becker;Tino Teige
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
6.A Matter of Overhead – Response Time Analysis of Hard Real-Time Systems in Theory and Practice

机译：理论与实践中硬实时系统的架空响应时间分析问题
- 作者：Max Brand;Albrecht Mayer;Frank Slomka
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
7.Exploration of DDR5 with the Open-Source Simulator DRAMSys

机译：DDR5与开源模拟器DRAMSYS的探索
- 作者：Lukas Steiner;Matthias Jung;Norbert Wehn
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
8.Comprehensive modeling and evaluation of Network-on-Chip performability

机译：综合建模与芯片交换性能的综合建模与评估
- 作者：Jie Hou;Martin Radetzki
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
9.Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications

机译：基于决策树的吞吐量估计，以加速多核应用的设计空间探索
- 作者：Martin Letras;Joachim Falk;Juergen Teich
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
10.ICP and IC3 with Stronger Generalization

机译：ICP和IC3具有更强的泛化
- 作者：Felix Winterer;Tobias Seufert;Karsten Scheibler;Tino Teige;Chritsoph Scholl;Bernd Becker
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年
11.Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

机译：RISC-V的约束随机验证：概述，评估和讨论
- 作者：Sallar Ahmadi-Pour;Vladimir Herdt;Rolf Drechsler
- 会议名称：《Workshop on Methods and Description Languages for the Modeling and Verification of Circuits and Systems》 | 2021年