Reducing Power in Wireless Design through Sequential Clock Gating

摘要

Advances in broadband wireless technology are driving low-power SoC design. The increasing digital content in these devices is necessitating the need for low-power design methods. Sequential analysis of RTL identifies powerful sequential clock gating optimizations that reduce dynamic power without changing functionality or impacting timing. PowerPro CG automates the sequential clock gating process, reducing power without impacting design area or timing.