Power modeling for high-level power estimation

摘要

In this paper, we propose a modeling approach that captures thendependence of the power dissipation of a combinational logic circuit onnits input/output signal switching statistics. The resulting powernmacromodel, consisting of a single four-dimensional table, can be usednto estimate the power consumed in the circuit for any given input/outputnsignal statistics. Given a low-level (typically gate-level) descriptionnof the circuit, we describe a characterization process by which such antable model can be automatically built. The four dimensions of ourntable-based model are the average input signal probability, averageninput transition density, average spatial correlation coefficient, andnaverage output zero-delay transition density. This approach has beennimplemented and models have been built for many benchmark circuits. Overna wide range of input signal statistics, we show that this model givesnvery good accuracy, with an rms error of about 4% and average error ofnabout 6%. Except for one out of about 10 000 cases, the largest errornobserved was under 20%. If one ignores the glitching activity, then thenrms error becomes under 1%, the average error becomes under 5%, and thenlargest error observed in all cases is under 18%