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Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression

机译:MPEG-4 AVC / H.264视频压缩的帧间总线编码技术和体系结构

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In this paper, we propose an implementation of a data encoder to reduce the switched capacitance on a system bus. Our technique focuses on transferring raw video data for multiple reference frames between off- and on-chip memories in an MPEG-4 AVC/H.264 encoder. This technique is based on entropy coding to minimize bus transition. Existing techniques exploit the correlation between neighboring pixels. In our proposed technique, we exploit pixel correlation between two consecutive frames. Our method achieves a 58% power saving compared to an unencoded bus when transferring pixels on a 32-b off-chip bus with a 15-pF capacitance per wire.
机译:在本文中,我们提出了一种数据编码器的实现方案,以减少系统总线上的开关电容。我们的技术着重于在MPEG-4 AVC / H.264编码器的片外和片内存储器之间为多个参考帧传输原始视频数据。该技术基于熵编码以最小化总线转换。现有技术利用了相邻像素之间的相关性。在我们提出的技术中,我们利用两个连续帧之间的像素相关性。当在32b片外总线上以每线15pF电容传输像素时,与未编码总线相比,我们的方法可实现58%的功耗节省。

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