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High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

机译:通过低温减压化学气相沉积获得高应变嵌入SiGe

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Performance improvement of strained p-type metal oxide semiconductor field effect transistors (p-MOSFETs) via embedded SiGe (e-SiGe) is well established. Strain scaling of p-MOSFETs since 90 nm complementary metal oxide semiconductor node has been accomplished by increasing Ge content in e-SiGe from nominally <20% in 90 nm p-MOSFETs to >35% Ge in 32 nm p-MOSFETs. Further strain enhancement for 22 nm and beyond p-MOSFETs is required due to disproportionate reduction in device area per generation caused by non-scaled gate length. Relaxation of SiGe with > 35% Ge during epitaxial growth and subsequent processing is a major concern. Specifically low temperature growth is required to achieve meta-stable pseudomorphic SiGe film with high Ge%. Currently, selective SiGe epitaxial film in reduced pressure chemical vapor deposition (RPCVD) epitaxy is grown with conventional Si gas precursors and co-flow etch using HC1 at temperatures higher than 625 ℃. At temperatures lower than 625 ℃ in RPCVD epitaxy, however, HCl has negligible etch capability making selectivity difficult to achieve during epitaxial growth. Hence, cyclic deposit and etch epitaxial growth in conjunction with a low temperature etching chemistry is desirable to achieve selectivity at temperatures lower than 625 ℃. In this paper, we apply the above concept to achieve selective growth of high strain SiGe (>35%) at 500 ℃ on test patterns corresponding to 65 nm node. SiGe is grown non-selectively first at 500 ℃ with high order of silane as Si source, and Germane as Ge source followed by an etching chemistry also at 500 ℃ to achieve selectivity. In addition, the growth rate of SiGe epitaxial film and the Ge concentration in the deposited epitaxial film were studied as a function of Si precursor flow; the effect of HC1 introduction on Ge concentration and film growth rate was discussed.
机译:通过嵌入式SiGe(e-SiGe)改善了应变p型金属氧化物半导体场效应晶体管(p-MOSFET)的性能已得到公认。通过将e-SiGe中的Ge含量从90 nm p-MOSFET中的标称<20%增加到32 nm p-MOSFET中的> 35%的锗,实现了90 nm互补金属氧化物半导体节点以来的p-MOSFET应变缩放。由于不按比例缩放的栅极长度导致每代器件面积的不成比例的减小,因此需要进一步增强22 nm以及超过p-MOSFET的应变。在外延生长和随后的加工过程中,锗含量大于35%的SiGe弛豫是一个主要问题。为了获得具有高Ge%的亚稳态伪晶SiGe膜,特别需要低温生长。目前,在减压化学气相沉积(RPCVD)外延中的选择性SiGe外延膜与常规的Si气体前驱体一起生长,并在625℃以上的温度下使用HCl进行共流蚀刻。然而,在RPCVD外延中低于625℃的温度下,HCl的蚀刻能力可忽略不计,使得在外延生长期间难以实现选择性。因此,希望在低于625℃的温度下实现选择性淀积和蚀刻外延生长并结合低温蚀刻工艺。在本文中,我们应用上述概念在对应于65 nm节点的测试图案上,在500℃下实现高应变SiGe(> 35%)的选择性生长。 SiGe首先在500℃下非选择性生长,其中高阶硅烷作为Si源,而锗烷则作为Ge源,然后在500℃下进行蚀刻化学以实现选择性。另外,研究了SiGe外延膜的生长速率和沉积的外延膜中Ge的浓度与Si前驱体流量的关系。讨论了HCl的引入对Ge浓度和膜生长速率的影响。

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