Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors

摘要

The application of chromeless phase-shift masks to sub-100nm gate length SOI transistor fabrication has achieved considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The maskmaking process uses a simple, single-step dry etch with no minimum geometry features, thus simplifying mask fabrication. In wafer fabrication, using just a 0.6 NA 248nm lithography tool and commercially available resists and antireflection layers, researchers achieved lithography results for k_1 factors down to 0.10 for isolated features and 0.3 for dense features. This corresponds to 40nm (isolated) and 125nm (dense) CDs on the stepper, or λ/6 and λ/2 resolutions, respectively. Excellent pattern transfer into polysilicon was achieved using a high-density plasma etch process producing gate features down to 25nm linewidths (k_1 = 0.06, or λ/10 resolution). The net results were sub-100nm gate-length fully depleted SOI CMOS transistors with excellent short-channel behavior down to 50nm physical gate lengths.