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Spin-etch planarization for dual damascene interconnect structures

机译:双镶嵌互连结构的自旋蚀刻平面化

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摘要

Dielectric erosion is an existing issue for copper damascene chemical mechanical planarization even when hard dielectric materials such as dense SiO_2 are used. A non-contact, non-slurry planarization process would provide distinct advantages for existing technologies as well as for future-generation, porous, ultra-low-k dielectrics that will be more susceptible to mechanical damage during chemical mechanical planarization. One such process in development is "spin-etch planarization," a wet-etch process using no physical contact with the wafer surface. Progress on this work is presented here.
机译:即使使用硬质介电材料(例如致密SiO_2),介电腐蚀也是铜镶嵌化学机械平坦化的现有问题。非接触,非浆液的平面化工艺将为现有技术以及未来的多孔,超低k介电质提供明显的优势,这些介电质在化学机械平面化过程中将更容易受到机械损伤。开发中的一种这样的工艺是“自旋蚀刻平坦化”,即不与晶片表面物理接触的湿法蚀刻工艺。这里介绍了这项工作的进展。

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