Shallow and abrupt junction formation: Paradigm shift at 65-70nm

摘要

The low-temperature (550-750℃) solid phase epitaxial method of forming shallow junctions is an attractive activation technique for the 65-70nm node and beyond. This novel method can be easily integrated into devices that are formed using a disposable spacer, or into low power CMOS devices using high-k dielectrics. With the continued growth trends in portable devices -along with their precursors, desktop computers - more and more emphasis is being placed on improving low power CMOS devices. This is driving the switch from oxynitride-type gate dielectrics with polysilicon electrodes, to high-k (HfO_2) dielectrics with metal electrodes by 2005, to satisfy the sub-90nm technology node.