For DRAM and logic: CVD low-k dielectric integration

摘要

Issues associated with the integration of CVD low-k dielectrics for 100nm technology node applications are described, including key fifm properties and factors determining successful integration into advanced DRAM and logic interconnect schemes. Advanced dynamic random access memory (DRAM), logic, and system-on-chip (SOC) manufacturers are increasingly using low-k dielectric materials to reduce parasitic capacitances in device interconnects. Use of CVD processing offers an evolutionary approach to the introduction of low-k intermetal dielectrics (IMDs) with a transition from plasma enhanced CVD (PECVD) SiO_2 (k>4) to so-called organo-silicate glass (OSG) materials (k<3).