Fabrication techniques and trends

摘要

Introduced as an alternative CMOS technology in 1978, silicon-on-insulator (SOI) offered the potential for high speed, low power consumption, soft-error reduction, latch-up immunity, manufacturing process simplification, and improved scaling. While SOI material was initially used in small niche markets, the opportunity for mainstream use has significantly broadened. During the last few years, it has serviced a variety of leading-edge IC applications such as microprocessors, servers, smart power, and RF signal processors, typically with partially depleted(PD) silicon layers. With MOS transistor scaling of the physical channel length (L_g) to the sub-50nm regime - en route to the sub-10 nm regime - alternative CMOS device structures [i.e., fully depleted (FD) ultrathin body], in conjunction with multiple gate configurations such as the FinFET with high- k gate dielectrics, metal electrodes, elevated source-drain, and strained silicon channels, will significantly broaden the opportunity for mainstream utilization of SOI.