Porous dielectrics

摘要

As the semiconductor industry approaches the 45nm process-technology node, the capacitance of the copper interconnect must be reduced to lower the RC delay and increase chip performance. The International Technology Roadmap for Semiconductors (ITRS) predicts that the industry will require a k value ≤ 2.2 at 45nm for interlevel dielectric materials. The primary method of lowering the dielectric constant is to make the dielectric film less dense by introducing porosity, which causes the film to become more fragile — leading to reliability and yield issues when these low-k dielectrics are incorporated into the Cu dual-damascene process. These reliability issues also greatly affect the packaging of completed devices.