Gaining synergy with strained silicon

摘要

Strained silicon is one of the key technology boosters identified by the International Technology Roadmap for Semiconductors (ITRS) as being essential to the continuation of classical scaling. The enhanced carrier mobilities made possible through strain engineering result in noteworthy device performance improvements. Current candidates for high-k gate dielectrics cause significant carrier degradation in the channel, and high-mobility channels will be needed to restore the losses. Without strained Si, high-k transistors will have no performance improvement over transistors with conventional gate oxides.