Addressing 32nm half-pitch challenges with double-patterning lithography

摘要

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning lithography (DPL) techniques have been proposed to address this limitation. This article discusses promising interim solutions for DPL control.