Co-implantation and RTA

摘要

Blanket and device wafer studies have been conducted to verify the benefits of USJs formed by co-implantation with conventional spike anneal. C co-implant improves the junction depth, profile abruptness, and concentration of the diffusion shoulder (which is indicative of the dopant activation) for both PMOS and NMOS transistors. Devices with C co-implanted SDEs exhibit better $ short channel effects and S/D resistance, consistent with the one-dimensional benefits. Finally, SSRM images confirm that the lateral boron diffusion ofboth the SDE and HDD is greatly reduced with co-implant.