Using wafer success rate metrics for analyzing cycle time

摘要

Traditionally semiconductor manufacturers have used two main methods to increase fab productivity. The first has been to implement changes such as continued device scaling and the move toward larger wafer sizes. The second method has been to rely on incremental technological improvements in tool capability. However, as scaling becomes more difficult and the cost of 300mm fabs escalates, manufacturers must put a similar effort into identifying and addressing the impact of even routine impediments to fab productivity and, particularly, the impact these have on cycle time. One technique is to use a comprehensive fab simulation model to determine the impact of such factors as wafer success rate improvements.