Model-based mask verification on 45nm logic gate masks

摘要

In the continuous battle to improve critical dimension (CD) uniformity, especially for 45nm advanced logic products, one important recent advance is the ability to accurately verify the mask CD uniformity contribution to the overall global wafer CD error budget. By establishing a mask bias model (MBM), we are able to incorporate the mask CD uniformity signature into our modeling simulations and measure the effects on global wafer CD uniformity and hot spots. We also have examined several ways of proving the efficiency of this approach.