Kicking off this year's SEMICON West, IMEC said it has been able to achieve electrically functional 32nm SRAM cells (FinFETs). The fin and gate levels were prepared using immersion lithography, but the contact hole level was exposed using EUV lithography (hole size 50nm). The work was done on ASML's alpha tool installed at IMEC. Although this work has been done at 45nm and 32nm, the ultimate target is for a production-worthy EUV tool at 22nm. "Memory companies will most likely insert EUV at 22nm to obtain the required half-pitch, while many logic manufacturers will be able to delay EUV insertion until the 16nm node, which for them corresponds to a 22nm half-pitch," explained Kurt Ronse, program director, advanced lithography, at IMEC, in an interview with SST.
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机译：IMEC表示，已经开始实现今年的SEMICON West，已经能够实现具有电功能的32nm SRAM单元（FinFET）。鳍和栅能级使用浸没式光刻法制备，而接触孔能级通过EUV光刻法（孔径50nm）曝光。这项工作是在IMEC上安装的ASML alpha工具上完成的。尽管这项工作已经在45nm和32nm上完成，但最终目标是在22nm上生产出值得生产的EUV工具。 “内存公司很可能会在22nm处插入EUV以获得所需的半间距，而许多逻辑制造商将能够将EUV插入推迟到16nm节点，这对他们来说相当于22nm半间距，” Kurt Ronse解释说， IMEC高级光刻技术程序总监在接受SST采访时。
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