System-in-package integration of passives using $ 3D through-silicon vias

摘要

Future generations of cellular RF transceivers require higher degrees of integration, preferably using the third dimension. System-in-Package (SiP) applications have been shown for integrated 3D "trench" capacitors in silicon with a new world record capacitance density of ≥ 400nF/mm~2 and break-down voltage > 6V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (AI_2O_3) and conductive layers (TiN). Different techniques may be used for through-silicon via (TSV) drilling and filling to allow for 3D die and wafer stacking with a small form factor. Both dry and wet-chemical methods were applied successfully in both the drilling and filling. Photo-electrochemical etching yields ultrafine high aspect ratio (～1.5μm×200μm) vias. A new "bottom-up" Cu-electroplating method and some preliminary Cu-paste filling tests show options for via metal formation.