Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM

摘要

Applying foundries' recommended design rules can often raise design costs because many recommended design rules result in trade-offs, requiring designers to spend more time in verification. In addition, as these rules are applied to every structure in the design, it often results in bigger die size. A silicon-aware design methodology can be used to evaluate intelligent design trade-offs and identify potential failures due to systematic manufacturing defects during the design phase. Applying a silicon-coutour-based method will be increasingly important as designers move into 45nm designs and beyond.