Optimization of edge die yield through detectivity reduction

摘要

In the pursuit of maximum productionrnefficiency, advanced semiconductor manufacturers are developing strategies to improve the yield of devices all the way to the wafer's edge. The ITRS shows edge exclusion decreasing from 3mm to 2mm currently, and to 1.5mm in the future [1], ultimately producing more dies out per wafer. This reduction in edge exclusion, along with several other process trends, is exacerbating edge-related productivity issues, making edge-related defects a priority for IC manufacturers. Here, we examine several approaches to reduce wafer edge defect sources.