Is 3D packaging where it needs to be?

摘要

More than a hundred attendees gathered at a Suss MicroTec workshop at this year's SEMICON West ("3D Integration: Are we there yet?") to hear technical experts from around the globe to present updates on the status of 3D IC packaging. Eric Beyne of IMEC addressed the technical issues of carrier systems for 3D through-silicon via (TSV) thinning and backside processing, pointing out that right now silicon carriers are favored over glass because: (1) the glass must be CTE matched to silicon over a large temperature range, (2) the high cost of ground to tight TTV specification, and (3) a negative effect on plasma-based post-grinding backside processes due to its low thermal conductivity.