BEOL technology at 20nm half-pitch

摘要

Integration of 20nm half-pitch (hp) interconnect structures will differ considerably from the state-of-the-art 28nm logic interconnect structures in terms of patterning, low-fc, and metallization. If 193nm immersion lithography is employed, double patterning will be adopted for the creation of damascene patterns. To restore the properties of the Si based low-k in the narrow spacing, which was modified during plasma etch and ash, additional treatments will be required. Alternative low-k dielectrics need to be considered to reduce the plasma modification. As for metallization, alternatives to the incumbent Ta-based barrier and Cu seed need to be developed to enable void free gap fill and to provide low resistance and sufficient reliability margin.