Thin die stacking for wide I/O memory-on-logic

摘要

Wide I/O interface memory-on-logic has the potential to be the long awaited killer application that will boost through silicon vias (TSVs) and 3D integration into high-volume manufacturing. Information transfer is rapidly transforming from text based communication to picture and video-based communication, which creates an insatiable demand for bandwidth. The convergence of smart phone and media server requires DRAM bandwidth >12GB/s in order to allow streaming of 1080p HD videos onto large displays. Conventional memory-logic interfaces ("narrow I/O interface") consume too much power at the input/outputs (I/Os) and do not allow scaling to multiple hundreds or thousands of I/Os. TSVs enable a significant power reduction at the I/O. Current DDR3 technology consumes 40mW per pin, whereas I/Os based on TSVs only consume 24 μW per pin [1]. This power reduction by 100 Ox gives chip designers the freedom to implement 512 I/Os with the next device generation.