Metallization processes for standardized wide-10 memory applications

摘要

Wide-IO memory is attracting substantial interest in the portable electronics space, with good reason - it combines performance enhancements and a smaller form factor with potential for substantial cost savings and reduced power consumption. Through-silicon vias (TSVs) are an important enabler for wide 10, and there is significant movement towards standardization of via structures, most likely on a via-last process with vias lOum wide by 50 deep. Metallization of this type of structure poses a number of technical and economic challenges to existing deposition processes. This article will explore the pros and cons of several possible approaches, and propose a process flow that offers cost and performance capabilities that can help realize the outstanding potential of wide 10 in the most effective way.