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The basics of copper, low-k and 3D interconnects

机译:铜,低k和3D互连的基础知识

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摘要

Copper lines offer less resistance and higher current-carrying capability than the previously used aluminum lines, but at small geometries surface scattering effects increase the effective resistivity, which has led to interest in alternative conductors such as graphene and carbon nanotubes. Standard silicon dioxide insulator (or dielectric) around the lines creates a high parasitic capacitance at narrow spacings with concomitant signal delays and increased power consumption. This had led to the introduction of and continued search for substitute materials. A dielectric's relative permittivity is expressed as "k." The lower the k, the faster the signal propagation speed and the lower the power consumption. (Vacuum, the perfect low permittivity material, has k=1; silicon dioxide has k~4.) The challenge with dielectric materials with very low k-values is that they are porous and generally more fragile than oxide dielectrics. Carbon-doped oxide (or SiCOH) low k dielectrics can be easily damaged by typical chip-making processes such as exposure to harsh plasma during photoresist-stripping and to chemical-mechanical polishing, used to planarize each interconnect layer.
机译:铜线比以前使用的铝线具有更少的电阻和更高的载流能力,但是在较小的几何形状下,表面散射效应会提高有效电阻率,这引起了人们对石墨烯和碳纳米管等替代导体的兴趣。线路周围的标准二氧化硅绝缘体(或电介质)在狭窄的间隔处会产生高寄生电容,并伴有信号延迟和功耗增加。这导致引入并继续寻找替代材料。电介质的相对介电常数表示为“ k”。 k越低,信号传播速度越快,功耗也越低。 (真空是一种理想的低介电常数材料,k为1;二氧化硅为k〜4。)具有非常低的k值的介电材料所面临的挑战是,它们比氧化物电介质更多孔且更易碎。碳掺杂氧化物(或SiCOH)低k电介质很容易被典型的芯片制造工艺损坏,例如在光刻胶剥离过程中暴露于苛刻的等离子体中以及用于平坦化每个互连层的化学机械抛光中。

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  • 来源
    《Solid state technology》 |2014年第3期|17-17|共1页
  • 作者

  • 作者单位
  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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  • 入库时间 2022-08-18 01:34:47

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