Low-k dielectric costs for dual-damascene integration

摘要

Low-k dielectric materials and processes for ULSI interconnection were sorted to create generic Cu dual-damascene process flows. Average material and equipment costs were then used as inputs to a generic cost-per-wafer (CPW) model for dielectric deposition (not including the costs of dielectric CMP, metallization, or lithography). Despite being completely different processes, both CVD and spin-on dielectric produce competitively priced films in the 2.3-3.0 k range. The generic model outputs are useful for comparing specific processes.