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Strained Si on insulator technology: from materials to devices

机译:绝缘体上应变硅技术:从材料到器件

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SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 A by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are maintained during anneals as long as 80 min at 1100℃. Fully depleted n-MOSFET electrical results show that biaxial tensile strain, and hence enhanced mobility, is fully maintained in the 400 A 20% SSOI films through the substrate and device fabrication processes, even after a generous FET fabrication thermal budget. Long channel devices exhibit nearly ideal subthreshold slopes of 66 mV/decade and exhibit 112% electron mobility enhancements at N_(inv) = 1 x 10~(13) cm~(-2), identical to devices on bulk strained Si substrates. Furthermore, a photoemission microscopy study was used to confirm that the useable SSOI layer thickness significantly exceeds the critical thickness for fabrication of bulk strained Si FETs without deleterious leakage current effects. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator is an ideal platform for future generations of Si-based microelectronics.
机译:不含SiGe的绝缘体上应变硅(SSOI)是一种新材料系统,结合了应变硅的载流子传输优势,减小的电容和改进的绝缘体上薄膜硅(SOI)的可扩展性。我们展示了通过高质量诱导的SiGe虚拟衬底的应变Si层的氢诱导层转移,制造了厚度分别为100和400 A的20%Ge等效应变水平的SSOI衬底。基材性能优异:晶圆级应变Si膜厚度均匀度优于8%,应变Si表面粗糙度优于0.5 nm RMS,并且在1100℃的退火过程中保持长达80分钟的稳定的拉伸应变水平。完全耗尽的n-MOSFET电学结果表明,即使经过大量的FET制造热预算,在整个衬底和器件制造过程中,400 A 20%SSOI膜也能完全保持双轴拉伸应变,从而提高迁移率。长沟道器件在N_(inv)= 1 x 10〜(13)cm〜(-2)时表现出近乎理想的亚阈值斜率(66 mV /十倍),并且电子迁移率提高了112%,与体应变Si衬底上的器件相同。此外,通过光电子显微镜研究证实了可用的SSOI层厚度大大超过了制造体应变Si FET的临界厚度,而没有有害的漏电流效应。直接在埋入式绝缘体上制造外延定义的薄应变Si层是下一代基于Si的微电子技术的理想平台。

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