Device design and manufacturing issues for 10 nm-scale MOSFETs: a computational study

摘要

The ITRS high performance NMOS device for the year 2016 (L_G = 9 nm) has been investigated using a 2D quantum simulator, NanoMOS-2.5. A device design methodology is introduced that gives the maximum on-current for a specified off-current, subject to a set of process conditions. Simulation results suggest that most of the targets can be met, but the on-current target will be challenging. In order to meet the on-current target while keeping the supply voltage at 0.4 V, enhancement of the source/drain contacts and the channel mobility are necessary at the same time. On the other hand, either by increasing the power supply to 0.5 V or by using a hi-k gate dielectric with EOT of 5 A, the on-current target should be achievable. Several design challenges have been identified such as a process tolerance requirement within 10% of the body thickness and an extremely sharp doping profile with a doping gradient of 1 nm/ decade.