Modelling of the 1T-Bulk capacitor-less DRAM cell with improved performances: The way to scaling

摘要

As capacitor-less DRAM cell appears to be an interesting candidate for future embedded memory generations, we paid particular attention to overall performance and scalability of the 1T-Bulk concept. We have analysed this architecture through our analytical model. Then we have fabricated devices and we have measured the influence of different technological parameters: floating body doping level, gate length and gate oxide thickness. The 1T-Bulk cell is demonstrated to be a promising candidate for eDRAM applications up to the 45 nm technological node.