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A compact model describing the effect of p-buffer layer on the Ⅰ-V characteristics of 4H-SiC power MESFETs

机译:描述p缓冲层对4H-SiC功率MESFET的Ⅰ-V特性影响的紧凑模型

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摘要

The multiple-layer epitaxial wafer is widely adopted to promote the performance of 4H-SiC MESFET in microwave applications, in which the p-type buffer layer underlying the n-type active layer affects both the DC and the RF output characteristics significantly. An equivalent parameter is proposed in this paper to describe the effect of doping and thickness of the p-buffer layer on the pinch off voltage and the drain conductance of 4H-SiC MESFET, Also the trapping effects at the channel/buffer interface and in the buffer layer are discussed qualitatively. The simulations of the improved Ⅰ-Ⅴ model are compared with the measurements From the 4H-SiC MESFETs on semi-insulating and conductive substrates and good agreements are obtained.
机译:多层外延晶片被广泛采用来提高4H-SiC MESFET在微波应用中的性能,其中n型有源层下面的p型缓冲层会显着影响DC和RF输出特性。本文提出了一个等效参数来描述p-缓冲层的掺杂和厚度对4H-SiC MESFET的夹断电压和漏极电导率的影响,以及沟道/缓冲界面和沟道中的俘获效应。定性地讨论了缓冲层。将改进的Ⅰ-Ⅴ模型的仿真结果与在半绝缘和导电衬底上的4H-SiC MESFET的测量结果进行比较,并获得了良好的一致性。

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