首页> 外文期刊>Solid-State Electronics >Modeling The Equivalent Oxide Thickness Of Surrounding Gate Soi Devices With High-κ Insulators
【24h】

Modeling The Equivalent Oxide Thickness Of Surrounding Gate Soi Devices With High-κ Insulators

机译:用高κ绝缘子模拟围栅soi器件的等效氧化物厚度

获取原文
获取原文并翻译 | 示例
       

摘要

In this work, the behavior of the gate insulator capacitance of different Surrounding Gate SOI devices with square and circular cross-sections has been studied. It is shown that the equivalent oxide thickness used for planar devices is not valid for devices with bidimensional confinement. For this kind of devices, new expressions for the gate insulator capacitance and equivalent oxide thickness are obtained using an approximate model of metal-insulator-metal capacitors. These expressions depend not only on the dielectric constant but also on the geometry of the device under consideration since for non-planar devices geometry plays an important role in the behavior of the C-V characteristics. The new expressions are validated by numerical simulations of these Multiple-Gate (MuG) devices that take into account quantum effects.
机译:在这项工作中,研究了具有方形和圆形横截面的不同围栅SOI器件的栅绝缘体电容行为。结果表明,用于平面器件的等效氧化物厚度对于具有二维约束的器件无效。对于这种器件,使用金属-绝缘体-金属电容器的近似模型可以获得栅极绝缘子电容和等效氧化物厚度的新表达式。这些表达式不仅取决于介电常数,还取决于所考虑器件的几何形状,因为对于非平面器件,几何形状在C-V特性的行为中起着重要作用。这些表达式已通过考虑了量子效应的这些多门(MuG)器件的数值模拟而得到验证。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号