Use of A1_2O_3 as inter-poly dielectric in a production proven 130 nm embedded Flash technology

摘要

We have successfully integrated 2Mb arrays with SiO_2/Al_2O_3 stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al_2O_3 grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high-κ IPD. Despite several integration issues, these results demonstrate the high potential of Al_2O_3 IPDs in embedded Flash technologies.