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Fully-depleted Ge Interband Tunnel Transistor: Modeling And Junction Formation

机译:Ge耗尽型带间隧道晶体管:建模和结形成

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Complementary fully-depleted Ge interband-tunneling field-effect transistors (TFETs) and static inverters are modeled to quantify TFET performance relative to Si MOSFETs. SYNOPSYS TCAD is used to compute the two-dimensional electrostatics and determine the tunnel junction electric field. This electric field is used in an analytic expression to compute the tunnel current. The speed and power performance of TFETs are compared with the nMOSFET at the same supply voltage, 0.5 V. For a gate length of 20 nm, Ge tunnel transistors can provide similar speed in comparison to 45-nm-node nMOSFETs (18 nm gate length), but saves more than 2× in power and lowers energy by over 7×. Toward demonstrating these transistors, a process for forming submicron p~+n~+ Ge tunnel junctions has been utilized in which Al-doped p~+ Ge is regrown on n~+ Ge, following melt-back of a patterned Al deposition. Transmission electron microscopy (TEM) reveals the regrown film and a contact microstructure consistent with the Al-Ge phase diagram. The low peak-to-valley current ratio (PVR) of devices produced by this growth method is likely a result of point defects or junction doping non-uniformity as TEM suggest no dislocations at the regrown junction. The PVR of these junctions does not improve as the device area is reduced from 100 to 0.1 μm~2, a size smaller than the formation scale for grains in the Al-Ge system.
机译:对互补的全耗尽Ge带间隧道场效应晶体管(TFET)和静态反相器进行建模,以量化相对于Si MOSFET的TFET性能。 SYNOPSYS TCAD用于计算二维静电并确定隧道结电场。该电场在解析表达式中用于计算隧道电流。在相同的电源电压0.5 V下,将TFET的速度和功率性能与nMOSFET进行了比较。对于栅极长度为20 nm的Ge隧道晶体管,与节点为45 nm的nMOSFET(栅极长度为18 nm)相比,可以提供相似的速度),但可节省超过2倍的功率,并降低7倍以上的能量。为了说明这些晶体管,已经采用了形成亚微米p + + n + Ge隧道结的工艺,其中在图案化的Al沉积物的熔回之后,在n + Ge上再生长Al掺杂的p + Ge。透射电子显微镜(TEM)揭示了再生长的薄膜和与Al-Ge相图一致的接触显微结构。通过这种生长方法生产的器件的低峰谷电流比(PVR)可能是点缺陷或结掺杂不均匀的结果,因为TEM表明再生长的结没有位错。当器件面积从100减小到0.1μm〜2时,这些结的PVR不会提高,其尺寸小于Al-Ge系统中晶粒的形成尺度。

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