Modelling and optimization of III/V transistors with matrices of nanowires

摘要

The magnitude and impact of the parasitic capacitances in a vertical In As nanowire transistor consisting of a matrix of nanowires is evaluated. A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated. Simulations of the S-parameters indicate an intrinsic f_T of about 690 GHz for 50 nm L_G. We show that f_T reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes. Finally, the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators.